SAB9082 データシートの表示（PDF） - Philips Electronics
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SAB9082 Datasheet PDF : 24 Pages
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Philips Semiconductors
NTSC Picture-In-Picture (PIP) controller
Preliminary specification
SAB9082
SYMBOL
n.c.
VSSD(RP)
VSSD(T8) and VSSD(T9)
VDDD(P2)
VSSD(P2)
VSSD(D)
VDDD(D)
FBL
PKOFF
DVSYNC
DCLK
SVSYNC
SCL
SDA
POR
VDDA(SA)
VSSA(SA)
VDDA(SF)
SU
Vref(B)(SA)
SV
Vref(T)(SA)
SY
Vbias(SA)
VSSD(SA)
VDDD(SA)
SHSYNC
T6
VDDA(SP)
VSSA(SP)
VSSA(DP)
VDDA(DP)
T7
DHSYNC
VDDD(MA)
VSSD(MA)
Vbias(MA)
MY
Vref(T)(MA)
MV
PIN
52 to 60
61
62 and 63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TYPE
−
S
S
S
S
S
S
O
O
I
I
I
I/O
I/O
I
S
S
S
I
I/O
I
I/O
I
I/O
S
S
I
I/O
S
S
S
S
I/O
I
S
S
I/O
I
I/O
I
DESCRIPTION
not connected
digital ground for memory periphery
digital ground for test
digital supply voltage for periphery
digital ground for periphery
digital ground for digital core
digital supply voltage for digital core
fast blanking control signal output (CMOS levels; +5 V tolerant)
peak off control signal output (CMOS levels; +5 V tolerant)
vertical sync display channel input (CMOS levels; +5 V tolerant)
test clock input (28 MHz; CMOS levels)
vertical sync for subchannel input (CMOS levels; +5 V tolerant)
input/output serial clock (I2C-bus; CMOS levels; +5 V tolerant)
input/output serial data/acknowledge output (I2C-bus; +5 V tolerant)
power-on reset input (CMOS levels; pull-up resistor connected to VDD)
analog supply voltage for subchannel ADCs
analog ground for subchannel ADCs
analog supply voltage for subchannel front-end buffers and clamps
analog U input for subchannel
input/output analog bottom reference voltage for subchannel ADCs
analog V input for subchannel
input/output analog top reference voltage for subchannel ADCs
analog Y input for subchannel
analog bias reference voltage for subchannel ADCs
digital ground for subchannel ADCs
digital supply voltage for subchannel ADCs
horizontal sync input for subchannel (Vi < VSHSYNC)
test data input/output bit 7 (CMOS levels)
analog supply voltage for subchannel PLL
analog ground for subchannel PLL
analog ground for display channel PLL
analog supply voltage for display channel PLL
test data input/output bit 6 (CMOS levels)
horizontal sync input for display channel (Vi < VDHSYNC)
digital supply voltage for main channel ADCs
digital ground for main channel ADCs
analog bias reference voltage for main channel ADCs
analog Y input for main channel
analog top reference voltage for main channel ADCs
analog V input for main channel
1999 Nov 12
5
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