PDM34078SA10QATY データシートの表示（PDF） - Paradigm Technology

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PDM34078SA10QATY

3.3V 32K x 32 Fast CMOS Synchronous Static RAM with Burst Counter and Output Register

Paradigm Technology 

PDM34078

Read Timing Diagram

tCYC

CLK

ADSP

tADSS

tCL

tCH

ADSC

tADSH

ADDRESS

ADV

GW, BWE

BW4-BW1

CE

OE

DATAOUT

tAS

A1

tAH

A2

tAAS

tAAH

tCES

tWS

tCEH

tCZ

tOE

tOLZ

tOHZ

Q1A1

tWH

tCQ

Q1A2

tCQX

Q2 A2

Q3 A3

A3

Q3 A2

tCZ

Q4 A2

Q2 A2

NOTES: 1. Qn(A2) refers to output from address A2. Q1–4 refers to outputs according to burst sequence.

2. CE2 and CE2 have timing identical to CE. In this diagram, when CE is low, CE2 is low and CE2 is high. When CE is high,

CE2 is high and CE2 is low.

10

Rev 1.0 - 5/01/98

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