PDM34089SA10QATR データシートの表示（PDF） - Paradigm Technology
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PDM34089SA10QATR
Paradigm Technology
PDM34089SA10QATR Datasheet PDF : 15 Pages
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PRELIMINARY
PDM34089
Synchronous Truth Table (See Notes 1 through 3)
CE CE2 CE2 ADSP ADSC ADV BWx CLK Address Operation
HXX
X
L
X
X
↑
N/A
Deselected
1
LXL
L
X
X
X
↑
N/A
Deselected
LHX
L
X
X
X
↑
N/A
Deselected
LXL
H
L
X
X
↑
N/A
Deselected
2
LHX
H
L
X
X
↑
N/A
Deselected
L LH
L
X
X
X
↑
External Read Cycle, Begin Burst
L LH
H
XXX
H
L
X
X
↑
External Read Cycle, Begin Burst
H
L
H
↑
Next Read Cycle, Continue Burst
3
HXX
X
H
L
H
↑
Next Read Cycle, Continue Burst
XXX
H
HXX
X
H
H
H
↑
Current Read Cycle, Suspend Burst
H
H
H
↑
Current Read Cycle, Suspend Burst
4
L LH
H
L
X
L
↑
External Write Cycle, Begin Burst
XXX
H
H
L
L
↑
Next Write Cycle, Continue Burst
HXX
X
H
L
L
↑
Next Write Cycle, Continue Burst
5
XXX
H
H
H
L
↑
Current Write Cycle, Suspend Burst
HXX
H
H
H
L
↑
Current Write Cycle, Suspend Burst
NOTES:
6
1. X = Don’t Care, H = logic High, L = logic Low, BWx = any one or more byte write enable signals (BW1, BW2, BW3, BW4)
and BWE are low, or GW is low.
2. BW1 enables BWx to Byte 1 (DQ1-DQ8). BW2 enables BWx to Byte 2 (DQ9-DQ16).
7 BW3 enables BWx to Byte 3 (DQ17-DQ24), BW4 enables BWx to Byte 4 (DQ25-DQ32).
3. ADV must always be high at the rising edge of the first clock after an ADSP cycle is initiated if a write cycle is desired (to
ensure use of correct address).
8
9
10
11
12
Rev 1.1 - 5/01/98
5
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