PDM34088SA10QTY データシートの表示（PDF） - Paradigm Technology

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PDM34088SA10QTY

3.3V 64K x 32 Fast CMOS Synchronous Static RAM with Burst Counter and Output Register

Paradigm Technology 

PRELIMINARY

PDM34088

Write Timing Diagram

tCYC

1

CLK

ADSP

tADSS

tCL

tCH

2

tADSH

ADSC

tAS

ADDRESS

A1

A2

tAH

tAAS

ADV

BWE(3)

BW4-BW1

tAAH

tWS

A3

3

4

tWH

tWS

GW(2)

5

tCES

tWH

CE

tCEH

6

OE

DATAIN

DATAOUT

tOHZ

D1 A1

D1 A2

D2 A2

D2 A2

D3 A2

D4 A2

D1 A3

D2 A3

tDS

D3 A3

D1 A1

tDH

7

8

NOTES: 1. CE2 and CE2 have timing identical to CE. On this diagram, when CE is low, CE2 is low and CE2 is high. When CE is high,

CE2 is high and CE2 is low.

2. Full width write can be initiated by GW low or GW high and BWE, BW1-BW4 low.

3 BWE is low when any one or more byte write enables (BW1-BW4) are low in this diagram.

9

10

11

12

Rev 2.1 - 5/01/98

11

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