MU9C8338 データシートの表示（PDF） - Music Semiconductors
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MU9C8338 Datasheet PDF : 28 Pages
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Pin Descriptions
MU9C8338 10/100Mb Ethernet Filter Interface
PIN DESCRIPTIONS
Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW.
Inputs should never be left floating. Refer to the Electrical Characteristics section for more information.
VDD
1
RP0
RP1
RP2
RP3
GND
6
RP4
RP5
RP6
VDD
RP7
RP8
12
RP9
RP10
RP11
RP12
GND
RP13
18
RP14
RP15
RP_DV
VDD
NC
SC_ENB
24
TST_HLD
GND
TST_HLD2
NC
VDD
RP_NXT
30
RP_SEL
GND
NC
NC
NC
GND
36
108
VDD
D15
NC
/RESET_LC
/W
/E
102
/CM
/EC
GND
/MI
/FI
VDD
96
DQ0
DQ1
GND
DQ2
DQ3
DQ4
90
DQ5
VDD
DQ6
NC
DQ7
DQ8
84
DQ9
DQ10
GND
DQ11
DQ12
DQ13
78
NC
DQ14
DQ15
GND
SYSCLK
NC
Figure 2: Pinout
MII Interface
RXD[3:0] (Receive Data, Input, TTL)
RXD[3:0] is the 4-bit MII Receive Data nibble (see
Timing Diagrams: Timing Data for RXD, RX_DV, and
RX_ER).
RX_DV (Receive Data Valid, Input, TTL)
Data Valid is on RX_DV; RX_DV is asserted by the PHY
at the beginning of the first nibble of the data frame and
deasserted at the end of the last nibble of the frame. It
indicates that the data is synchronous to RX_CLK and is
itself synchronous to the clock (see Timing Diagrams:
Timing Data for RXD, RX_DV, and RX_ER).
RX_ER (Receive Error, Input, TTL)
RX_ER indicates a data symbol error in 100Mb/s mode or
any other error that the PHY can detect, even if the MAC
is not capable of detecting that error (see Timing
Diagrams: Timing Data for RXD, RX_DV, and RX_ER).
RX_CLK (Receive Clock, Input, TTL)
RX_CLK is the receive clock recovered from the data by
the PHY. It is equal to 25MHz in 100Base-X mode or
2.5MHz in 10Base-X mode.
CRS (Carrier Sense, Input, TTL)
Carrier sense CRS indicates that the medium is active
(non-idle) and remains asserted during a collision. For Rx
or Tx: CRS is HIGH in 10/100Base-X half-duplex mode;
for Rx it is HIGH in repeater, full-duplex, and loopback
modes. CRS is not synchronized to RX_CLK.
Rev. 1a
3
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