MU9C8338 データシートの表示（PDF） - Music Semiconductors

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MU9C8338

10/100Mb Ethernet Filter Interface

Music Semiconductors 

MU9C8338 10/100Mb Ethernet Filter Interface

Pin Descriptions

COL (Collision, Input, TTL)

Collision detect COL is asserted by the PHY upon

detection of a collision on the medium and remains

asserted as long as the collision persists. It is HIGH in

half-duplex modes and remains HIGH for 1 microsecond

following the end of transmission; it is LOW in

full-duplex mode. It is asserted in response to

signal_quality_error message from the PMA in 10Base-X

Heartbeat mode.

Tag Port Interface

REJ (Reject, Output, TTL)

REJ is the reject packet command issued by the

MU9C8338. REJ is driven HIGH to reject a data frame,

and can be detected by and responded to by the MAC

device from 2 bit times after SFD to 512 bit times (64 byte

times) after SFD. The REJ signal can be made active

LOW by setting Bit 0 in the SSCFG register. (See Timing

Diagrams: REJ Timing Data.

FRX_ER (Frame Error, Output, TTL)

The Forced Receive Error pins provide the logical OR of

the RX_ER and REJ lines for the MII port (see Timing

Diagrams: Timing Data for FRX_ER in Relation to REJ

and RX_ER).

TP_SD (Tag Port Data, Output, TTL)

The Tag Port Serial Data pin carries the destination Port

ID to external circuitry as soon as it is collected from the

CAM (see Timing Diagrams: Timing Data for Tag Ports

TP_DV and TP_SD).

TP_DV (Tag Port Data Valid, Output, TTL)

The Tag Port Data Valid pin is driven HIGH for as long as

unread data exists for the Destination Port ID. Pin TP_SD

carries the Destination Port ID (6 bits) to external circuitry

as soon as it is collected from the CAM (see Timing

Diagrams: Timing Data for Tag Ports TP_DV and

TP_SD).

Result Port Interface

See Timing Diagrams: Timing Data for Result Port

Interface. Table 1 shows the Result Port bit descriptions.

Note: Although the result data register can also be read through

the processor port, it is important to note that the means of

retrieving the data must be unique. Therefore, if the user is not

using the Result Port Interface, but is reading result data through

the processor port, RP_NXT and RP_SEL should be pulled low.

This ensures that all result data remains in the Result Data

register until read through the processor port. RP_NXT and

RP_SEL should be pulled low to 0 volts through a pull-down

resistor (typically 10k ohms).

RP[15:0] (Result Port Data, Output, Tri-state, TTL)

The Result Port Data carries the results of recently

processed packets detected on the MII port. See Table 1

for details of the Result Port Data bit descriptions. These

are identical to the Result Data register bits.

RP_DV (Result Port Data Valid, Output TTL)

The Result Port Data Valid indicates that the RP port

carries valid packet data. As long as there is valid packet

data, RP_DV will stay HIGH.

RP_NXT (Result Port Next Data, Input, TTL)

The Result Port Next pin brings the next result to the RP

bus if RP_SEL is asserted. If there are no additional results

available, the RP_DV will drop LOW after the time

interval specified in the Result Port Timing specification.

RP_SEL (Result Port Select, Input, TTL)

The Result Port Select pin controls RP[15:0] and

RP_NXT. RP_NXT and RP_SEL are connected by a

logical AND. Therefore, RP_SEL must be HIGH in order

for RP_NXT to bring the next result to the RP bus.

RP_SEL can stay continuously HIGH as long as there is

valid packet data, RP_DV will stay HIGH.

Table 1: Result Port Bit Descriptions

Bit(s)

15:10

9:8

7

6:1

0

Description

6-Bit Source Port ID

Packet Type: Broadcast = 00, Multicast = 01,

Unicast = 10

(if Unicast) Match Found

6-Bit (if CAM Match Found) Destination Port ID

(If Match Found) Destination Port = Source Port

Control Interfaces

See Timing Diagrams: Timing Data for Control Interfaces.

SYSCLK (System Clock, Input, TTL)

CLK is the user-supplied system clock for synchronous

chip operation; its frequency must be 25-50 MHz with

duty cycle between 45 to 55 percent.

/RESET (Reset, Input, TTL)

When system Reset is taken LOW, all internal

state-machines are reset to their initial state and any data is

cleared. All registers are returned to default values.

/RESET is synchronous and should be held LOW for a

minimum of two SYSCLK cycles. The user must set the

LANCAM Segment Control register after asserting

/RESET.

4

Rev. 1a

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