VP310GQ1R データシートの表示（PDF） - Mitel Networks

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VP310GQ1R

Satellite Channel Decoder

Mitel Networks 

VP310

PRELIMINARY DATA

In DVB mode, spectrum de-scrambling is performed compatible with the DVB specification. The

final output is a parallel or serial transport data stream; packet sync; data clock; and a block error

signal. The data clock may be inverted under software control.

1.4.1.1 Viterbi error count measurement

A method of estimating the bit error rate at the output of the QPSK block has been provided in

the Viterbi decoder. The incoming data bit stream is delayed and compared with the re-encoded

and punctured version of the decoded bit stream to obtain a count of errors see Figure 2 below.

VITERBI

DECODER

DATA BIT STREAM

VITERBI

ENCODER

DELAY

COMP

ERROR COUNT

Figure 2. Viterbi block diagram.

The measurement system has a programmable register to determine the number of data bits (the

error count period) over which the count is being recorded. A read register indicates the error

count result and an interrupt can be generated to inform the host microprocessor that a new

count is available.

The VIT_ERRPER H-M-L group of three registers is programmed with required number of data

bits (the error count period) (VIT_ERRPER[23:0]). The actual value is four times

VIT_ERRPER[23:0]. The count of errors found during this period is loaded by the VP310 into the

VIT_ERRCNT H-M-L trio of registers when the bit count VIT_ERRPER[23:0] is reached. At the

same time an interrupt is generated on the IRQ line. Setting the IE_FEC[2] bit in the IE_FEC

register enables the interrupt. Reading the register does not clear VIT_ERRCNT [23:0], it is only

loaded with the error count.

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