VP310GQ1R データシートの表示（PDF） - Mitel Networks

部品番号

コンポーネント説明

メーカー

VP310GQ1R

Satellite Channel Decoder

Mitel Networks 

VP310

VITERBI

COURSE

BIT

ERROR

COUNT

0

0

PRELIMINARY DATA

VIT_MAXERR[7:0]

DATA BITS

STATUS

Figure 4. Viterbi error count coarse indication.

1.4.2 The Frame Alignment block

The frame alignment algorithm detects a sequence of correctly spaced synchronising bytes in the

Viterbi decoded bit-stream and arranges the input into blocks of data bytes. Each block consists

of 204 bytes for DVB and 147 bytes for DSS. In the DSS mode, the synchronising byte is

removed from the data stream, so only 146 bytes of a block are passed to the next stage. The

frame alignment block also removes the 180° phase ambiguity not removed by Viterbi decoder.

1.4.3 The De-interleaver block

1.4.3.1 DVB

Before transmission, the data bytes are interleaved with each other in a cyclic pattern of twelve.

This ensures the bytes are spaced out to avoid the possibility of a noise spike corrupting a group

of consecutive message bytes. The diagram below shows conceptually how the convolutional de-

interleaving system works. The synchronisation byte is always loaded into the First-In-First-Out

(FIFO) memory in branch 0. The switch is operated at regular byte intervals to insert successively

received bytes into successive branches. After 12 bytes have been received, byte 13 is written

next to the synchronisation byte in branch 0, etc. In the VP310, this de-interleaving function is

realised using on-chip Random Access Memory (RAM).

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