LCX037BLT
∗3 Input video signal, and a uniformity improvement signal as shown phase like below. And the rise time trPsig
and the fall time tfPsig of Psig1 to 4 are suppressed within 400ns.
Phase relationship between video signal and uniformity improvement signal
Vsig1, 3, 5, 7, 9, 11
H blanking period
H effective period
Sig1, 3, 5, 7, 9, 11
Sig-Center
Vpsig1, 4
Sig-Center
Psig1
Psig4
Psig4
Psig1
Vsig2, 4, 6, 8, 10, 12
Time
Time
Sig-Center
Sig2, 4, 6, 8, 10, 12
Vpsig2, 3
Sig-Center
Psig3
Psig2
Psig2
Psig3
Time
Time
Level Conversion Circuit
The LCX037BLT has a built-in level conversion circuit in the clock input unit on the panel. The input signal
level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
–7–