CAT1021LI-25-G(2009) データシートの表示（PDF） - ON Semiconductor
部品番号
コンポーネント説明
メーカー
CAT1021LI-25-G
(Rev.:2009)
(Rev.:2009)
ON Semiconductor
CAT1021LI-25-G Datasheet PDF : 21 Pages
| |||
CAPACITANCE
TA = 25ºC, f = 1.0 MHz, VCC = 5 V
Symbol
COUT (1)
CIN(1)
Test
Output Capacitance
Input Capacitance
CAT1021, CAT1022, CAT1023
Test Conditions
VOUT = 0 V
VIN = 0 V
Max Units
8
pF
6
pF
AC CHARACTERISTICS
VCC = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol Parameter
Min
Max
fSCL
Clock Frequency
400
tSP
Input Filter Spike Suppression (SDA, SCL)
100
tLOW Clock Low Period
1.3
tHIGH
tR(1)
tF(1)
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
0.6
300
300
tHD; STA Start Condition Hold Time
0.6
tSU; STA Start Condition Setup Time (for a Repeated Start)
0.6
tHD; DAT Data Input Hold Time
0
tSU; DAT Data Input Setup Time
100
tSU; STO Stop Condition Setup Time
0.6
tAA
SCL Low to Data Out Valid
900
tDH
Data Out Hold Time
50
tBUF(1) Time the Bus must be Free Before a New Transmission Can Start
1.3
tWC(3) Write Cycle Time (Byte or Page)
5
Units
kHz
ns
µs
µs
ns
ns
µs
µs
ns
ns
µs
ns
ns
µs
ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© 2009 SCILLC. All rights reserved.
5
Characteristics subject to change without notice
Doc. No. MD-3009 Rev. P
Share Link: