CAT24C00 データシートの表示（PDF） - Catalyst Semiconductor => Onsemi

部品番号

コンポーネント説明

メーカー

CAT24C00

128-bit Serial EEPROM

Catalyst Semiconductor => Onsemi 

CAT24C00

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT24C00 monitors the

SDA and SCL lines and will not respond until this

condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master then sends the address

of the particular slave device it is requesting. The four

most significant bits of the 8-bit slave address are fixed

as 1010 for the CAT24C00 (see Fig. 5). The next three

significant bits are "don't care" bits. The last bit of the

slave address specifies whether a Read or Write operation

is to be performed. When this bit is set to 1, a Read

operation is selected, and when set to 0, a Write operation

is selected.

After the Master sends a START condition and the slave

address byte, the CAT24C00 monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT24C00 then performs a Read or Write operation

depending on the state of the R/W bit.

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge. The

Acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8 bits

of data.

Figure 4. Acknowledge Timing

The CAT24C00 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation,

it responds with an acknowledge after receiving each 8-

bit byte.

When the CAT24C00 is in a READ mode it transmits 8

bits of data, releases the SDA line, and monitors the line

for an acknowledge. Once it receives this acknowledge,

the CAT24C00 will continue to transmit data. If no

acknowledge is sent by the Master, the device terminates

data transmission and waits for a STOP condition.

WRITE OPERATION

Byte Write

In the Write mode, the Master device sends the START

condition and the slave address information (with the R/

W bit set to zero) to the Slave device. After the Slave

generates an acknowledge, the Master sends the byte

address that is to be written into the address pointer of

the CAT24C00. After receiving another acknowledge

from the Slave, the Master device transmits the data

byte to be written into the addressed memory location.

The CAT24C00 acknowledges once more and the

Master generates the STOP condition, at which time the

device begins its internal programming cycle to

nonvolatile memory. While this internal cycle is in

progress, the device will not respond to any request

from the Master device.

After a write command, the internal address counter

will continue to point to the same address location

that was just written. If a stop bit is transmitted to the

device at any point in the write sequence before the

entire sequence is complete, then the command will

abort and no data will be written. If more than eight

SCL FROM

1

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

5

8

9

ACKNOWLEDGE

5020 FHD F06

Doc. No. 1027, Rev. N

Share Link: