CAT25010 データシートの表示（PDF） - Catalyst Semiconductor => Onsemi
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CAT25010 Datasheet PDF : 17 Pages
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READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ
instruction followed by a 8-bit address (for the
CAT25040, bit 3 of the read instruction opcode
contains A8 address bit).
After receiving the last address bit, the
CAT25010/20/40 will respond by shifting out data on
the SO pin (as shown in Figure 8). Sequentially stored
data can be read out by simply continuing to run the
clock. The internal address pointer is automatically
incremented to the next higher address as data is
shifted out. After reaching the highest memory
address, the address counter “rolls over” to the lowest
memory address, and the read cycle can be continued
indefinitely. The read operation is terminated by taking
C¯¯S high.
CAT25010, CAT25020, CAT25040
Read Status Register
To read the status register, the host simply sends a
RDSR command. After receiving the last bit of the
command, the CAT25010/20/40 will shift out the
contents of the status register on the SO pin
(Figure 9). The status register may be read at any
time, including during an internal write cycle.
Figure 8. READ Timing
CS
SCK
0123456789
12 13 14 15 16 17 18 19 20 21 22
OPCODE
BYTE ADDRESS
SI
0 0 0 0 X* 0 1 1 A7
A0
SO
HIGH IMPEDANCE
Notes:
Dashed Line = mode (1, 1) - - - - - -
* X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
DATA OUT
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Figure 9. RDSR Timing
CS
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
OPCODE
SI
0
0
0
0
0
SO
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1) - - - - - -
1
0
1
DATA OUT
7
6
5
4
3
2
10
MSB
© Catalyst Semiconductor, Inc.
9
Characteristics subject to change without notice
Doc. No. MD-1006 Rev. T
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