CAT28C17AG-20T データシートの表示（PDF） - ON Semiconductor

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CAT28C17AG-20T

16 kb CMOS Parallel EEPROM

ON Semiconductor 

CAT28C17A

DEVICE OPERATION

Read

Data stored in the CAT28C17A is transferred to the data

bus when WE is held high, and both OE and CE are held low.

The data bus is set to a high impedance state when either CE

or OE goes high. This 2−line control architecture can be used

to eliminate bus contention in a system environment.

tRC

ADDRESS

tCE

CE

Ready/BUSY (RDY/BUSY)

The RDY/BUSY pin is an open drain output which

indicates device status during programming. It is pulled low

during the write cycle and released at the end of

programming. Several devices may be OR−tied to the same

RDY/BUSY line.

OE

WE

DATA OUT

tOE

VIH

tOLZ

tLZ

HIGH−Z

tAA

tOH

DATA VALID

Figure 4. Read Cycle

tOHZ

tHZ

DATA VALID

ADDRESS

CE

tAS

tAH

tCS

tWC

tCH

OE

WE

RDY/BUSY

DATA OUT

tOES

tWP

HIGH−Z

tOEH

tDL

tDB

DATA IN

DATA VALID

tDS

tDH

Figure 5. Byte Write Cycle [WE Controlled]

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