CAT28C17AGA-20T データシートの表示（PDF） - ON Semiconductor

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CAT28C17AGA-20T

16 kb CMOS Parallel EEPROM

ON Semiconductor 

CAT28C17A

Byte Write

A write cycle is executed when both CE and WE are low,

and OE is high. Write cycles can be initiated using either WE

or CE, with the address input being latched on the falling

edge of WE or CE, whichever occurs last. Data, conversely,

is latched on the rising edge of WE or CE, whichever occurs

first. Once initiated, a byte write cycle automatically erases

the addressed byte and the new data is written within 10 ms.

DATA Polling

DATA polling is provided to indicate the completion of a

byte write cycle. Once a byte write cycle is initiated,

attempting to read the last byte written will output the

complement of that data on I/O7 (I/O0–I/O6 are

indeterminate) until the programming cycle is complete.

Upon completion of the self−timed byte write cycle, all I/O’s

will output true data during a read cycle.

tWC

ADDRESS

tAS

CE

tAH

tCW

tDL

tOEH

OE

tOES

tCS

tCH

WE

RDY/BUSY

DATA OUT

tDB

HIGH−Z

DATA IN

DATA VALID

tDS

tDH

Figure 6. Byte Write Cycle [CE Controlled]

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