CAT93C86(2013) データシートの表示（PDF） - ON Semiconductor
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CAT93C86 Datasheet PDF : 10 Pages
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CAT93C86
Table 4. PIN CAPACITANCE (Note 5)
Symbol
Test
COUT
CIN
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
VOUT = 0 V
VIN = 0 V
Min
Typ
Max
Units
5
pF
5
pF
Table 5. POWER−UP TIMING (Notes 5, 6)
Symbol
Parameter
tPUR
tPUW
Power−up to Read Operation
Power−up to Write Operation
Max
Units
1
ms
1
ms
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤ 50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 x VCC to 0.7 x VCC
0.5 x VCC
4.5 V ≤ VCC ≤ 5.5 V
4.5 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC ≤ 4.5 V
1.8 V ≤ VCC ≤ 4.5 V
Table 7. A.C. CHARACTERISTICS
VCC =
1.8 V − 5.5 V
VCC =
2.5 V − 5.5 V
VCC =
4.5 V − 5.5 V
Symbol
Parameter
Test Conditions
Min Max Min Max Min Max
tCSS
CS Setup Time
200
100
50
tCSH
CS Hold Time
0
0
0
tDIS
DI Setup Time
200
100
50
tDIH
DI Hold Time
200
100
50
tPD1
Output Delay to 1
1
0.5
tPD0
Output Delay to 0
CL = 100 pF (Note 7)
1
0.5
tHZ (Note 5) Output Delay to High−Z
400
200
tEW
Program/Erase Pulse Width
5
5
tCSMIN
Minimum CS Low Time
1
0.5
0.15
tSKHI
Minimum SK High Time
1
0.5
0.15
tSKLOW
Minimum SK Low Time
1
0.5
0.15
tSV
Output Delay to Status Valid
1
0.5
SKMAX
Maximum Clock Frequency
DC 500 DC 1000 DC
5. These parameters are tested initially and after a design or process change that affects the parameter.
6. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
7. The input levels and timing reference points are shown in the “A.C. Test Conditions” table.
0.15
0.15
100
5
0.1
3000
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
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