CD4071BCN データシートの表示（PDF） - Fairchild Semiconductor

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CD4071BCN

CD4071BC Quad 2-Input OR Buffered B Series Gate • CD4081BC Quad 2-Input AND Buffered B Series Gate

Fairchild Semiconductor 

Schematic Diagrams

CD4071B

CD4081B

1/4 of device shown

J=A+B

Logical “1” = HIGH

Logical “0” = LOW

*All inputs protected by standard CMOS protection circuit.

1/4 of device shown

J=A•B

Logical “1” = HIGH

Logical “0” = LOW

All inputs protected by standard CMOS protection circuit.

www.fairchildsemi.com

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