CDP1802A データシートの表示（PDF） - Intersil

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CDP1802A

CMOS 8-Bit Microprocessors

Intersil 

CDP1802A, CDP1802AC, CDP1802BC

Timing Waveforms (Continued)

CLOCK

0

tW

00 01

1

10 11

2

20 21

3

30 31

4

40 41

5

50 51

6

60 61

7

0

70 71 00 01

TPA

tPLH

tPHL

TPB

MEMORY

ADDRESS

tPLH, tPHL

tSU

tH

HIGH ORDER

tPLH, tPHL

ADDRESS BYTE

MRD

(MEMORY

tPLH

READ CYCLE)

MWR

(MEMORY

WRITE CYCLE)

tPHL

tSU

tPLH

tPHL

DATA FROM

CPU TO BUS

LOW ORDER

ADDRESS BYTE

tPHL

tPLH

tPHL

tPLH, tPHL

tH

tPLH

tPLH

tH

tPLH, tPHL

STATE

CODES

tPLH

tPHL

Q

tPLH, tPHL

tPLH, tPHL

N0, N1, N2

tPLH

(I/O EXECUTION

CYCLE)

DATA FROM

BUS TO CPU

DMA

REQUEST

INTERRUPT

REQUEST

EF 1-4

FLAG LINES

SAMPLED (IN S1)

tSU tH

tPLH

DATA

LATCHED IN CPU

tSU

tH

DMA SAMPLED (S1, S2, S3)

tSU

tH

INTERRUPT

SAMPLED (S1, S2)

tSU

tH

WAIT

tSU

ANY NEGATIVE

TRANSITION

tW

CLEAR

NOTES:

1. This timing diagram is used to show signal relationships only and does not represent any specific machine cycle.

2. All measurements are referenced to 50% point of the waveforms.

3. Shaded areas indicate “Don’t Care” or undefined state. Multiple transitions may occur during this period.

FIGURE 4. TIMING WAVEFORM

3-12

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