CDP1802A データシートの表示（PDF） - Intersil

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CDP1802A

CMOS 8-Bit Microprocessors

Intersil 

CDP1802A, CDP1802AC, CDP1802BC

Machine Cycle Timing Waveforms (Propagation Delays Not Shown)

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 70

CLOCK

TPA

TPB

MACHINE

CYCLE

CYCLE n

CYCLE (n + 1)

CYCLE (n + 2)

MA

HIGH ADD

LOW ADDRESS

HIGH ADD

LOW ADDRESS

HIGH ADD

LOW ADDRESS

FIGURE 5. GENERAL TIMING WAVEFORMS

INSTRUCTION

MRD

FETCH (S0)

MEMORY READ CYCLE

EXECUTE (S1)

NON MEMORY CYCLE

FETCH (S0)

MEMORY READ CYCLE

MWR (HIGH)

MEMORY

OUTPUT

ALLOWABLE MEMORY ACCESS

VALID OUTPUT

“DON’T CARE” OR INTERNAL DELAYS

HIGH IMPEDANCE STATE

FIGURE 6. NON-MEMORY CYCLE TIMING WAVEFORMS

EXECUTE

VALID

OUTPUT

INSTRUCTION

MRD

MWR

FETCH (S0)

MEMORY READ CYCLE

EXECUTE (S1)

MEMORY WRITE CYCLE

FETCH (S0)

MEMORY READ CYCLE

EXECUTE

MEMORY

OUTPUT

CPU OUTPUT

TO MEMORY

ALLOWABLE MEMORY ACCESS

OFF

VALID OUTPUT

VALID DATA

“DON’T CARE” OR INTERNAL DELAYS

OFF

HIGH IMPEDANCE STATE

FIGURE 7. MEMORY WRITE CYCLE TIMING WAVEFORMS

VALID

OUTPUT

VALID

3-13

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