CMX635 データシートの表示（PDF） - CML Microsystems Plc

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CMX635

ISDN Subscriber Processor

CML Microsystems Plc 

ISDN Subscriber Processor

CMX635

AD[7:0]

Processor interface Address/Data bus. Bi-directional cmos level input/output bus that carries

multiplexed address and data when multiplexed mode is automatically detected by the CMX635

and data only when non-multiplexed mode is detected.

ASel

Address Select. Asel, when asserted, selects the internal indirect address register as the

destination for non-multiplexed processor read/writes, or the data register when de-asserted. Asel

may be connected to A[0] of the non-multiplexed processor address bus. Connect to Vss for

multiplexed interface operation.

Dtack

Data Acknowledge. Active only when the Motorola style multiplexed mode processor interface is

detected. It is an open drain output that is pulled low at the start of a processor read or write cycle

and remains low until the CMX635 internal cycle is complete. The Dtack signal can be used to

implement a hardware handshake cycle timing mechanism.

ALE

Address Latch Enable. The multiplexed address from the AD bus is latched on the falling edge of

ALE. Connect ALE to Vcc if an Intel style non-multiplexed interface is being used and to Vss for a

Motorola style non-multiplexed interface.

nWR

Write Strobe, active low. Latches the data from the AD bus on the rising edge in Intel style mode.

Acts as a R/nW strobe in Motorola mode. See the timing diagrams in section 1.8.1 for more

details on the nWR pin function.

nRD

Read Strobe, active low. Initiates a CMX635 read cycle and enables read data to be driven onto

the AD bus in Intel style mode. Acts as a DS or E strobe in Motorola style mode. See the timing

diagrams in section 1.8.1 for more details on the nWR pin function.

nCS

Chip Select, active low. Must be low for duration of read or write cycle in all interface modes.

Processor interface is inactive and will not respond to read/write strobe activity when nCS is high.

nIRQ

Interrupt Request, open drain. Pulled to Vss when the CMX635 internal Status Registers generate

an unmasked interrupt request. It remains in its high impedance state when no interrupts are

pending. An external pull-up resistor is required.

RESET

Global Chip Reset. Active high reset input resets CMX635 internal state and restores default

configuration. The RESET input should be asserted at power-up before any configuration is

written or modes activated. The RESET must be asserted until the oscillator input has stabilised

(either from a crystal or external clock source) to ensure full internal reset.

X1, X2

Oscillator input pins. A 12.288Mhz or 15.36MHz crystal may be connected between these pins

(see External Components section 1.4) or an external clock source may be connected to X1 with

X2 connected to Vss.

© 2001 Consumer Microcircuits Limited

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D/635/2

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