CMX649 データシートの表示（PDF） - CML Microsystems Plc

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CMX649

ADM Codec

CML Microsystems Plc 

ADM Codec

CMX649

should be programmed to be 1/10th of the ADM bit rate (or lower) for “toll” (or better) quality audio

reconstruction. For “communications” quality, the audio bandwidth may approach 1/6th of the ADM bit

rate for ADM rates below 20kbps. The anti-alias/image SC filter bandwidth is programmed directly via C-

BUS commands to the AAF/AIF BANDWIDTH Register ($61). Additionally, the switched capacitor clock

frequency can be altered via C-BUS commands to the CLK DIVIDER CONTROL Register ($72).

Typically, the CLK DIVIDER CONTROL Register should be programmed to provide a 256kHz SC filter

clock. Altering the SC filter clock from the recommended 256kHz frequency proportionally scales the

frequency axis in the plot below:

20

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

1,000

10,000

Frequency (Hz)

B W = 14 . 0 k H z

B W = 10 . 0 k H z

BW=7.0kHz

BW=5.0kHz

BW=3.7kHz

BW=2.9kHz

100,000

Figure 10a Typical Anti-Alias/Image Filter Frequency Response

© 2003 CML Microsystems Plc

10

D/649/2

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