CMX813 データシートの表示（PDF） - CML Microsystems Plc
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CMX813 Datasheet PDF : 21 Pages
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Multi-Standard Analogue Paging Decoder
CMX813
STATUS Register (Hex address $3F)
This register is used to indicate the status of the device as described below:
(Bits 7, 6 and 5)
Reserved for future use. These will be set to "110" respectively but should be
ignored by user's software.
RAM FULL
(Bit 4)
After eight tone addresses are loaded to the RAM for tones located in ROM
PAGE 1 or 2, this bit is set to ‘1’. A Clear RAM command will reset it to ‘0’.
DECODE STATUS
CHANGE
(Bit 3)
When TONE DECODE (Bit 2 of this register) or the decoded 8 bit address in
DECODED TONE ADDRESS Register $38 changes state this bit will be set to
"1". A “0” indicates no decode status change.
TONE DECODE
(Bit 2)
This bit indicates the status of the tone decoder. A "1" indicates a tone has
been detected (TONE DECODE) and a "0" indicates the loss of the tone
(NOTONE).
TONE DECODE means that a tone has been decoded and its characteristics
are as defined by the bandwidth (see CONTROL Register $30, Bits 5, 4, 3
and 2) and the centre frequency ( see TONE ADDRESS Register $31, Bit 7 to
Bit 0).
When Bit 7 and Bit 6 in the CONTROL Register $30 are set to "0" the TONE
DECODE Bit 2 will be set to "0".
From NOTONE state, identification of a valid tone which is not in the pre-
programmed list (up to eight tones in 1 or 2 tone system and 16 tones in 5/6
tone or HSC) will cause the decoder to move to the TONE DECODE state
with the DECODED ROM PAGE address of "00" in Bits 1 and 0; indicating a
valid but unrecognised tone. No interrupt is generated.
Loss of tone will cause the NOTONE timer to be started. If loss of tone
continues for the duration of the time-out period, then the decoder will move
to the NOTONE state and the identification of pre-programmed tones will start
again. The time-out period is not user adjustable.
DECODED ROM
PAGE
(Bits 1 and 0)
These two bits represent the ROM PAGE where the decoded tone is located.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
DECODED ROM PAGE
A valid but unrecognised tone
Decoded tone in ROM Page 1
Decoded tone in ROM Page 2
Decoded tone in ROM Page 3
If the DECODE STATUS CHANGE (Bit 3) of the STATUS Register is ‘1’ or the RAM FULL (Bit 4) of the
STATUS Register changes from ‘0’ to ‘1’ then the IRQN output will be pulled low.
Reading the STATUS register clears the interrupt (IRQN output pulled high) and also clears Bit 3 of the
STATUS Register, if set. A Clear RAM command clears Bit 4 of the STATUS Register, if set.
In Zero Power mode, Status Register Bits 7 to 0 are preset to “110x0000” respectively. RAM FULL (Bit 4)
remains undisturbed.
© 2000 Consumer Microcircuits Limited
10
D/813/33
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