CMX850 データシートの表示（PDF） - CML Microsystems Plc
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CMX850 Datasheet PDF : 103 Pages
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Communications Controller
CMX850
Package
L8
35
36
37
38
39
40
41
Signal
DVSS
P5.0 (KBC.8)
P5.1 (KBC.9)
P5.2 (KBC.10)
P5.3 (KBC.11)
P5.4 (KBC.12)
DVDD
42
D0 : P5.5 (KBC.13)
43
D1 : P5.6 (KBC.14)
44
D2 : P5.7 (KBC.15)
45
D3 : P0.0
46
D4 : P0.1
47
D5 : P0.2
48
D6 : INT9
49
D7 : ALE
50
DVSS
51
A0 : AD0
52
A1 : AD1
53
A2 : AD2
54
A3 : AD3
55
A4 : AD4
56
A5 : AD5
57
A6 : AD6
58
A7 : AD7
59
DVDD
60
A8
61
A9
62
A10
63
A11
64
A12
65
A13
66
A14
67
A15
Power
BI
BI
BI
BI
BI
Power
BI : BI
BI : BI
BI : BI
BI : BI
BI : BI
BI : BI
BI : I/P
BI : O/P
Power
O/P : BI
O/P : BI
O/P : BI
O/P : BI
O/P : BI
O/P : BI
O/P : BI
O/P : BI
Power
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
Description
The digital negative supply rail (ground).
Port 5 bits 4-0. Alternative function is keyboard column drivers,
bits 12-8. Unused column drivers remain as general-purpose
port pins.
The digital positive supply rail.
With pin MUXAD tied to DVSS:
Bi-directional data bus for
external memory.
With pin MUXAD tied to DVDD:
Port 5 bits 7-5. Alternative
function is keyboard column
drivers, bits 15-13. Unused
column drivers remain as
general-purpose port pins.
Port 0 bits 2-0.
Super priority interrupt (active
low). When configured as an
interrupt, this pin should be
fitted with a 100kΩ pullup
resistor to DVDD (not shown in
Figure 2a), if driven by an
open-drain driver.
Address latch enable.
The digital negative supply rail (ground).
With pin MUXAD tied to DVSS: With pin MUXAD tied to DVDD:
External memory interface
address bus (LSB).
External memory interface
multiplexed address (LSB)
and data. While ALE is high,
the LSB of the memory
address is driven out. When
ALE goes low, the pins
change to a bi-directional
data bus.
The digital positive supply rail.
External memory interface address bus (MSB).
© 2003 CML Microsystems Plc
7
D/850/6
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