CS4614 データシートの表示（PDF） - Cirrus Logic
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CS4614 Datasheet PDF : 24 Pages
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CS4614
CrystalClear™ SoundFusion™ PCI Audio Accelerator
PCI INTERFACE PINS (TA = 0 to 70° C; PCIVDD = CVDD = CRYVDD = 3.3 V; VDD5REF = 5 V;
PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V)
Parameter
PCICLK cycle time
PCICLK high time
PCICLK low time
PCICLK to signal valid delay - bused signals
PCICLK to signal valid delay - point to point
Float to active delay
(Note 13)
Active to Float delay
(Note 13)
Input Set up Time to PCICLK - bused signals
Input Set up Time to PCICLK - point to point
Input hold time for PCICLK
Reset active time after PCICLK stable
(Note 14)
Reset active to output float delay
(Notes 13, 14, 15)
Symbol
tcyc
thigh
tlow
tval
tval(p+p)
ton
toff
tsu
tsu(p+p)
th
trst-clk
trst-off
Min
30
11
11
2
2
2
-
7
10, 12
0
100
-
Max
Unit
-
ns
-
ns
-
ns
11
ns
12
ns
-
ns
28
ns
-
ns
-
ns
-
ns
-
µs
40
ns
Notes: 13. For Active/Float measurements, the Hi-Z or “off” state is when the total current delivered is less than or
equal to the leakage current. Specification is guaranteed by design, not production tested.
14. RST# is asserted and de-asserted asynchronously with respect to PCICLK.
15. All output drivers are asynchronously floated when RST# is active.
PCICLK
RST#
t rst-clk
t off
t on
OUTPUTS
Hi-Z
t val
OUTPUTS
Valid
t rst-off
t su
INPUTS
th
Valid
Input
Figure 2. PCI Timing Measurement Conditions
DS292PP3
CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM
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