CS5165AGDWR16G データシートの表示（PDF） - ON Semiconductor
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CS5165AGDWR16G Datasheet PDF : 18 Pages
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CS5165A
ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC < 14 V; 2.8 DAC Code:
(VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0); CGATE(H) and CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 mF, unless otherwise specified.)
Characteristic
VCC Supply Current
Operating
Test Conditions
1.0 V < VFB < VDAC (max on−time)
No Loads on GATE(H) and GATE(L)
Min
Typ
Max
Unit
−
12
20
mA
Sleep Mode
VCC Monitor
Start Threshold
Stop Threshold
Hysteresis
Error Amplifier
VFB Bias Current
COMP Source Current
COMP CLAMP Voltage
COMP Clamp Current
COMP Sink Current
Open Loop Gain
Unity Gain Bandwidth
PSRR @ 1.0 kHz
ENABLE = 0 V
−
GATE(H) switching
3.75
GATE(H) not switching
3.65
Start−Stop
−
VFB = 0 V
−
COMP = 1.2 V to 3.6 V; VFB = 2.7 V
15
VFB = 2.7 V, Adjust COMP voltage for Comp current = 50 mA 0.85
COMP = 0 V
0.4
VCOMP = 1.2 V; VFB = 3.0 V; VSS > 2.5 V
180
(Note 2)
50
(Note 2)
0.5
(Note 2)
60
300
3.95
3.87
80
0.1
30
1.0
1.0
400
60
2.0
85
600
mA
4.15
V
4.05
V
−
mV
1.0
mA
60
mA
1.15
V
1.6
mA
800
mA
−
dB
−
MHz
−
dB
GATE(H) and GATE(L)
High Voltage at 100 mA
Low Voltage at 100 mA
Rise Time
Fall Time
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE pulldown
Measure VCC − GATE
Measure GATE
1.6 V < GATE < (VCC − 2.5 V)
(VCC − 2.5 V) > GATE > 1.6 V
GATE(H) < 2.0 V; GATE(L) > 2.0 V
GATE(L) < 2.0 V; GATE(H) > 2.0 V
Resistor to PGND, (Note 2)
−
1.2
2.0
V
−
1.0
1.5
V
−
40
80
ns
−
40
80
ns
30
65
100
ns
30
65
100
ns
20
50
115
kW
Fault Protection
SS Charge Time
SS Pulse Period
SS Duty Cycle
VFB = 0 V
VFB = 0 V
(Charge Time/Period) × 100
1.6
3.3
5.0
ms
25
100
200
ms
1.0
3.3
6.0
%
SS COMP Clamp Voltage
VFB Low Comparator
VFB = 2.7 V; VSS = 0 V
Increase VFB till no SS pulsing and normal Off−time
0.50
0.95
1.10
V
0.9
1.0
1.1
V
PWM Comparator
Transient Response
VFB = 1.2 to 5.0 V. 500 ns after GATE(H)
−
130
180
ns
(after Blanking time) to GATE(H) = (VCC −1.0 V) to 1.0 V
Minimum Pulse Width
(Blanking Time)
Drive VFB. 1.2 to 5.0 V upon GATE(H) rising edge
(> VCC − 1.0 V), measure GATE(H) pulse width
50
150
250
ns
COFF
Normal Off−Time
Extended Off−Time
VFB = 2.7 V
VSS = VFB = 0 V
1.0
1.6
2.3
ms
5.0
8.0
12.0
ms
Time−Out Timer
Time−Out Time
Fault Duty Cycle
Enable Input
VFB = 2.7 V, Measure GATE(H) Pulse Width
VFB = 0V
10
30
50
ms
30
50
70
%
ENABLE Threshold
GATE(H) Switching
0.8
1.15
1.30
V
Shutdown delay (Note 3)
ENABLE−to−GATE(H) < 2.0 V
−
3.0
−
ms
2. Guaranteed by design, not 100% tested in production.
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