CS5451A-ISZ(2005) データシートの表示（PDF） - Cirrus Logic

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CS5451A-ISZ
(Rev.:2005)

Six-channel, Delta-sigma Analog-to-digital Converter

Cirrus Logic 

CS5451A

4. FUNCTIONAL DESCRIPTION

4.1 Analog Inputs

The CS5451A is equipped with six fully differential input

channels. The inputs VIN(1-3)± and IIN(1-3)± are des-

ignated as the voltage and current channel inputs, re-

spectively. The full-scale differential input voltage for

the current and voltage channel is ±800 mVP

(gain = 1x).

4.1.1 Voltage Channel

The output of the line voltage resistive divider or trans-

former is connected to the VIN(1-3)+ and VIN(1-3)- in-

put pins of the CS5451A. The voltage channels are

equipped with a 1x fixed gain amplifier. The full-scale

signal level that can be applied to the voltage channel is

±800 mV. If the input signal is a sine wave the maximum

RMS voltage is:

8---0---0--m----V---P--

2

≅

565.69mVRMS

which is approximately 70.7% of maximum peak volt-

age.

4.1.2 Current Channel

The output of the current sense resistor or transformer

is connected to the IIN(1-3)+ and IIN(1-3)- input pins of

the CS5451A. To accommodate different current-sens-

ing devices the current channels incorporates a pro-

grammable gain amplifier (PGA) that can be set to one

of two input ranges. Input pin GAIN (see Table 1) define

the PGA’s two gain selections and corresponding max-

imum input signal level.

GAIN

0

1

Maximum Input Range

±40mV

20x

±800mV

1x

Table 1. Current Channel PGA Setting

4.2 Digital Filters

The decimating digital filter samples the modulator bit

stream at XIN/8 and produces a fixed output word rate.

The digital filters are implemented as sinc3 filters with

the following transfer function:

H(z)

=

⎛

⎜

⎝

-1--1--–---–--z--z-–--–-D--1--R- ⎠⎟⎞

3

The decimation rate is determined by the exponent DR

(see Table 2).

The output word rate (OWR) is selected by the OWRS

pin and defined by Table 2.

OWRS

DR Output Word Rate

0

256

1

128

XIN/2048

XIN/1024

Table 2. Decimation Filter OWR

4.3 Performing Measurements

The ADC outputs are transferred in 16-bit, signed (two’s

complement) data formats. Table 3 defines the relation-

ship between the differential voltage applied to any one

of the input channels and the corresponding output

code. Note that for the current channels, the state of the

GAIN input pin is assumed to driven low such that the

PGA gain on the current channels is 1x. If the PGA gain

of the current channels is set to 20x, a +40 mV voltage

is applied to any pair of IIN(1-3)± pins would cause an

output code of 32767.

Differential Input Output Code

Voltage (mV) (hexadecimal)

+800

7FFF

0.0122 to 0.0366

0001

-0.0122 to 0.0122

0000

-0.0122 to -0.0366

FFFF

-800

8000

Notes: Assume PGA gain is set to 1x.

Output Code

(decimal)

32767

1

0

-1

-32768

Table 3. Differential Input Voltage vs. Output Code

4.4 Serial Interface

The CS5451A communicates with a target device via a

master serial data output port. Output data is provided

on the SDO output synchronous with the SCLK output.

A third output, FSO, is a framing signal used to signal

the start of output data. These three outputs will be driv-

en as long as the SE (serial enable) input is held high.

Otherwise, these outputs will be high-impedance.

Data out (SDO) changes as a result of SCLK falling, and

always outputs valid data on the rising edge of SCLK.

When data is being transferred the SCLK frequency is

XIN/8 when OWRS is low or XIN/4 when OWRS is high.

DS635F2

9

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