CS5504 データシートの表示（PDF） - Cirrus Logic
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CS5504 Datasheet PDF : 24 Pages
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CS5504
CS5504
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Symbol Min
Typ
Max Units
Serial Clock
fsclk
0
-
2.5 MHz
Serial Clock
Pulse Width High
Pulse Width Low
tph
200
-
tpl
200
-
-
ns
-
ns
Access Time:
CS Low to data valid (Note 15) tcsd
-
60
200
ns
Maximum Delay Time:
(Note 16)
SCLK falling to new SDATA bit tdd
-
150
310
ns
Output Float Delay:
CS high to output Hi-Z (Note 17) tfd1
-
60
150
ns
SCLK falling to Hi-Z tfd2
-
160
300
ns
Notes: 15. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To
guarantee proper clocking of SDATA when using asynchronous CS, SCLK should not be taken high
sooner than 2/fclk + 200 ns after CS goes low.
16. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.
17. If CS is returned high before all data bits are output, the SDATA output will complete the current data
bit and then go to high impedance.
3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VD+ = 3.3V ±
5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Symbol Min
Typ
Max Units
Serial Clock
fsclk
0
-
1.25 MHz
Serial Clock
Pulse Width High
Pulse Width Low
tph
200
-
tpl
200
-
-
ns
-
ns
Access Time:
CS Low to data valid (Note 15) tcsd
-
100
200
ns
Maximum Delay Time:
(Note 16)
SCLK falling to new SDATA bit tdd
-
400
600
ns
Output Float Delay:
CS high to output Hi-Z (Note 17) tfd1
-
70
150
ns
SCLK falling to Hi-Z tfd2
-
320
500
ns
DS126F12
7
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