CS5541 データシートの表示（PDF） - Cirrus Logic

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CS5541

Low-Power, Low-Voltage, 24-Bit ∆Σ ADC

Cirrus Logic 

CS5541

2. GENERAL DESCRIPTION

The CS5541 is a 24-bit, low-power and low-volt-

age ∆−Σ analog-to-digital converter (ADC). It is

optimized to convert analog signals in DC mea-

surement applications such as temperature and

pressure measurement, and various portable devic-

es where low power consumption is required.

To accommodate these applications, the ADC inte-

grates analog input and reference buffers for in-

creased input impedance and includes a

two-channel multiplexer. Absolute accuracy is

achieved via one-time or continuous calibration

modes. The device also operates with a variety of

supply configurations while drawing less than 330

µA.

The CS5541 includes two digital filters. The first

filter which achieves simultaneous rejection of

50/60 Hz provides single conversion settling at

13.4 SPS throughput or four conversion settling at

53.7 SPS throughput. The second filter which

achieves 16-bit performance provides single con-

version settling at 64.8 SPS throughput or four con-

version settling at 260 SPS throughput. (Either

filter’s output word rates can be increased by using

a faster master clock, up to 40 kHz).

To ease communication between the ADCs and a

microcontroller, the converters include a simple

three-wire serial interface which is SPI and Mi-

crowire compatible. A Schmitt Trigger input is pro-

vided on the serial clock (SCLK) input.

2.1 Analog Input

Figure 4 illustrates a block diagram of the CS5541.

The device consists of a multiplexer, a unity gain

coarse/fine charge input buffer, a fourth order ∆−Σ

modulator, and a digital filter.

2.1.1 Analog Input Model

Figure 5 illustrates the input models for the AIN

pins. The model includes a coarse/fine charge buff-

er which reduces the dynamic current demand on

the analog input signal. The buffer is designed to

accommodate rail to rail (common-mode plus sig-

nal) input voltages. Typical CVF (sampling) cur-

rent is about 12 nA (MCLK = 32.768 kHz).

Application Note 30, “Switched-Capacitor A/D In-

put Structures”, details various input architectures.

in = CV osf

AIN

φ1 Fine

φ 2 Coarse

Vos ≤ 25mV

C = 8 pF

f = 2*MCLK = 65.536 kHz

Figure 5. Input model for AIN+ and AIN- pins.

AIN1+

X1

AIN1-

M

U

AIN2+

X

X1

AIN2-

VREF+ VREF-

X1 X1

Differential

4 th Order

∆Σ

Modulator

Sinc4

Digital

Filter

Serial

Port

CS

SDI

SDO

SCLK

Figure 4. Multiplexer Configuration.

10

DS500PP1

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