CS5560-ISZ(2008) データシートの表示（PDF） - Cirrus Logic

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CS5560-ISZ
(Rev.:2008)

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Cirrus Logic 

3/25/08

CS5560

SWITCHING CHARACTERISTICS (CONTINUED)

TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.

Parameter

Symbol Min

Typ

Max Unit

Serial Port Timing in SSC Mode (SMODE = VL)

Data hold time after SCLK rising

t7

-

10

-

ns

Serial Clock (Out)

(Note 12, 13)

Pulse Width (low) t8

50

-

Pulse Width (high) t9

50

-

-

ns

-

ns

RDY rising after last SCLK rising

t10

-

8

- MCLKs

CS falling to MSB stable

t11

-

10

-

ns

First SCLK rising after CS falling

t12

-

8

- MCLKs

CS hold time (low) after SCLK rising

t13

10

-

-

ns

SCLK, SDO tristate after CS rising

t14

-

5

-

ns

12. SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resistor.

13. SCLK = MCLK/2.

MCLK

RDY

CS

SCLK(o)

SDO

t10

t13

t12

t7

t8

t9

t14

t11

MSB

MSB–1

LSB+1 LSB

Figure 2. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale)

8

DS713PP1

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