CS5560-ISZ(2008) データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CS5560-ISZ
(Rev.:2008)

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Cirrus Logic 

3/25/08

CS5560

SWITCHING CHARACTERISTICS

TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.

Parameter

Symbol Min

Typ

Master Clock Frequency

Internal Oscillator XIN

12

14

External Clock fclk

0.5

16

Master Clock Duty Cycle

40

-

Reset

RST Low Time

tres

1

-

RST rising to RDY falling

Internal Oscillator twup

External Clock

-

120

-

1536

Conversion

CONV Pulse Width

tcpw

4

-

BP/UP setup to CONV falling

(Note 7)

tscn

0

-

CONV low to start of conversion

tscn

-

-

Perform Single Conversion (CONV high before RDY falling)

tbus

20

-

Conversion Time

(Note 8)

Start of Conversion to RDY falling tbuh

-

-

Sleep Mode

SLEEP low to low-power state

tcon

SLEEP high to device active (Note 9)

tcon

-

50

-

3083

7. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.

8. If CONV is held low continuously, conversions occur every 320 MCLK cycles.

If RDY is tied to CONV, conversions will occur every 322 MCLKs.

If CONV is operated asynchronously to MCLK, a conversion may take up to 324 MCLKs.

RDY falls at the end of conversion.

9. RDY will fall when the device is fully operational when coming out of sleep mode.

Max

16

16.2

60

-

-

-

-

-

2

-

324

-

-

Unit

MHz

MHz

%

µs

µs

MCLKs

MCLKs

ns

MCLKs

MCLKs

MCLKs

µs

MCLKs

6

DS713PP1

Share Link: