CS5560-ISZ データシートの表示（PDF） - Cirrus Logic

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CS5560-ISZ

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Cirrus Logic 

7/31/07

CS5560

SWITCHING CHARACTERISTICS (CONTINUED)

TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

Parameter

Calibration Register Read Timing

CS hold time (high) after SCLK rising

Data setup time before SCLK rising

Data hold time after SCLK rising

SCLK rising to data stable

Data hold time after SCLK rising

SCLK rising to CS rising

SDO tristate after CS rising

Symbol Min

Typ

Max Unit

t22

10

-

t23

10

-

t24

10

-

t25

-

10

t26

-

10

t27

10

-

t28

-

5

ns

-

ns

-

ns

-

ns

-

ns

-

ns

-

ns

CS

SCLK(i)

SDI

SDO

t22

t27

t23

t24

MSB

LSB

Command Time

8 SCLKs

t25

t26

MSB

Data Time

24 SCLKs

t28

LSB

Figure 4. SEC Mode - Calibration Register Read Timing (Not to Scale)

10

DS713A5

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