CS5560-ISZ データシートの表示（PDF） - Cirrus Logic

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CS5560-ISZ

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Cirrus Logic 

7/31/07

CS5560

SWITCHING CHARACTERISTICS (CONTINUED)

TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

Parameter

Symbol Min

Typ

Max

Calibration Register Write Timing

Data setup time before SCLK rising

t29

10

-

-

Data hold time after SCLK rising

t30

10

-

-

SCLK rising to CS rising

t31

10

-

-

17. SDO will be high impedance when CS is high. In some systems it may require a pull-down resister.

Unit

ns

ns

ns

CS

SCLK(i)

SDI

t31

t29

t30

MSB

Command Time

8 SCLKs

LSB MSB

LSB

Data Time

24 SCLKs

Figure 5. SEC Mode - Write Timing (Not to Scale)

DS713A5

11

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