CS5566 データシートの表示（PDF） - Cirrus Logic

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コンポーネント説明

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CS5566

±2.5 V / 5 V, 5 kSps, 24-bit ΔΣ ADC

Cirrus Logic 

5/4/09

CS5566

MCLK

RDY

CS

SCLK(i)

SDO

t15

t17

t18 t19

MSB

t21

t20

LSB

Figure 5. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale)

DIGITAL CHARACTERISTICS

TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V

Parameter

Input Leakage Current

Digital Input Pin Capacitance

Digital Output Pin Capacitance

Symbol

Min

Typ Max Unit

Iin

-

-

2

µA

Cin

-

3

-

pF

Cout

-

3

-

pF

DIGITAL FILTER CHARACTERISTICS

TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V

Group Delay

Parameter

Symbol Min

(Note 16)

-

-

Typ

Max Unit

160

- MCLKs

16. See Figure 4 to understand conversion timing. The 160 MCLK group delay occurs during the 354 MCLK high-power period of a

conversion cycle. See Section 3.2 Power Consumption for more detail.

10

DS806PP2

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