CS5571(2007) データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CS5571
(Rev.:2007)

±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ∆Σ ADC

Cirrus Logic 

6/25/07

14:12

CS5571

SWITCHING CHARACTERISTICS (CONTINUED)

TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

Parameter

Symbol Min

Typ

Max

Serial Port Timing in SEC Mode (SMODE = VLR)

SCLK(in) Pulse Width (High)

-

30

-

-

SCLK(in) Pulse Width (Low)

-

30

-

-

CS hold time (high) after RDY falling

t15

10

-

-

CS hold time (high) after SCLK rising

t16

10

-

-

CS low to SDO out of Hi-Z

(Note 18) t17

-

10

-

Data hold time after SCLK rising

t18

-

10

-

Data setup time before SCLK rising

t19

10

-

-

CS hold time (low) after SCLK rising

t20

10

-

-

RDY rising after SCLK falling

t21

-

10

-

18. SDO will be high impedance when CS is high. In some systems it may require a pull-down resister.

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

MCLK

RDY

CS

SCLK(i)

SDO

t15

t16

t17

t18

t19

MSB

t21

t20

LSB

Figure 3. SEC Mode - Read Timing (Not to Scale)

DS768A5

9

Share Link: