CS61577-IL1Z データシートの表示（PDF） - Cirrus Logic
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CS61577-IL1Z Datasheet PDF : 30 Pages
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CS61577
#3
!.!,/' 30%#)&)#!4)/.3 (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
0ARAMETER
-IN
4YP
-AX
5NITS
2ECEIVER
RTIP/RRING Input Impedance
-
50k
-
Ω
Sensitivity Below DSX (0dB = 2.4V)
-13.6
-
500
-
-
dB
-
mV
Loss of Signal Threshold
-
0.30
-
V
Data Decision Threshold
T1, DSX-1
(Note 20)
60
65
70
% of peak
T1, DSX-1
(Note 21)
53
65
77
% of peak
T1, (FCC Part 68) and E1 (Note 22)
45
50
55
% of peak
Allowable Consecutive Zeros before LOS
160
175
190
bits
Receiver Input Jitter Tolerance
10kHz - 100kHz
2kHz
10Hz and below
(Note 23)
0.4
-
6.0
-
300
-
-
UI
-
UI
-
UI
*ITTER !TTENUATOR
Jitter Attenuation Curve Corner Frequency (Notes 17, 24)
-
6
-
Hz
Attenuation at 10kHz Jitter Frequency
(Notes 17, 24)
-
50
-
dB
Attenuator Input Jitter Tolerance (Before Onset
12
23
-
UI
of FIFO Overflow or Underflow Protection) (Notes 17, 24)
Notes: 20. For input amplitude of 1.2 Vpk to 4.14 Vpk.
21. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+.
22. For input amplitude of 1.05 Vpk to 3.3 Vpk.
23. Jitter tolerance increases at lower frequencies. See Figure 11.
24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates
jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase
significantly when more than 12 UI’s are input to the attenuator. See discussion in the text section.
4
$3DS15050F
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