CS61581(2005) データシートの表示（PDF） - Cirrus Logic
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CS61581 Datasheet PDF : 37 Pages
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CS61581
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0 V ±5%;
GND = 0 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol Min
Typ
Max
TCLK Frequency
ftclk
-
1.544
-
MCLK Frequency
(Note 19) fmclk
-
1.544
-
RCLK Duty Cycle
(Notes 18, 20) tpwh1/tpw1
50
Rise Time, All Digital Outputs
(Note 21)
tr
-
-
85
Fall Time, All Digital Outputs
(Note 21)
tf
-
-
85
TPOS/TNEG to TCLK Falling Setup Time
tsu2
25
-
-
TCLK Falling to TPOS/TNEG Hold Time
th2
25
-
-
RPOS/RNEG Valid Before RCLK Falling
(Note 22) tsu1
150
274
-
RPOS/RNEG Valid Before RCLK Rising
(Note 23) tsu1
150
274
-
RPOS/RNEG Valid After RCLK Falling
(Note 22)
th1
150
274
-
RPOS/RNEG Valid After RCLK Rising
(Note 23)
th1
150
274
-
Notes: 19. MCLK provided by an external source or TCLK.
20. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator FIFO limits are reached.
21. At max load of 1.6 mA and 50 pF.
22. Host Mode (CLKE = 1).
23. Host Mode (CLKE = 0)
Units
MHz
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0 V ±5%;
GND = 0 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
TCLK Frequency
MCLK Frequency
RCLK Duty Cycle
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TPOS/TNEG to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG Hold Time
RPOS/RNEG Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
Symbol Min
ftclk
-
(Note 19) fmclk
-
(Notes 18, 20) tpwh1/tpw1
(Note 21)
tr
-
(Note 21)
tf
-
tsu2
25
th2
25
(Note 22) tsu1
100
(Note 23) tsu1
100
(Note 22)
th1
100
(Note 23)
th1
100
Typ
2.048
2.048
50
-
-
-
-
194
194
194
194
Max
-
-
85
85
-
-
-
-
-
-
Units
MHz
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
DS211PF1P8
7
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