CS61581 データシートの表示（PDF） - Cirrus Logic

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CS61581

T1/E1 Universal Line Interface

Cirrus Logic 

CS61581

2.4.5 Jitter Tolerance

The receiver jitter tolerance is shown in Figure 8.

The CS61581 jitter tolerance exceeds AT&T

62411 in T1 applications, and G.823 in E1 applica-

tions.

2.5 Receiver Line Attenuation Indication

LATN (pin 18) outputs a coded signal that repre-

sents the signal level at the input of the receiver. As

shown in Figure 9, the LATN output is measured

against RCLK to provide the signal level in 7.5 dB

increments. In host mode, the receive input signal

level can be read from the Equalizer Gain register

(address 0x12), to greater resolution, dividing the

input range into 20 steps of 2 dB increments.

2.6 Jitter Attenuator

The jitter attenuator reduces the amount of jitter

and wander in the input signal. the jitter attenuator

is built around a FIFO; the write pointer of the

FIFO is driven by the input clock, and the read

pointer is driven by a phase locked loop (PLL). The

jitter attenuator can be placed in either the transmit

or receive paths; in the transmit path, writing to the

FIFO is controlled by TCLK; if the jitter attenuator

is in the receive path, writing is controlled by the

recovered clock from the input data. The jitter at-

tenuator does not require an external crystal. If a

crystal is present, the PLL uses it for a reference;

otherwise, MCLK provides the reference.

The jitter attenuator is enabled if an external crystal

is connected. If no crystal is present, then the jitter

attenuator is enabled by either grounding or float-

ing XTALIN (pin 9). It is disabled by tying

XTALIN high. It is placed in the transmit or re-

ceive paths by setting JASEL (pin 11) either low or

high, respectively.

The jitter attenuator has two modes of operation de-

pending on whether the CS61581 is configured for

T1 or E1 operation (based on the output pulse

shape selection). For T1, the jitter attenuator corner

frequency is set at 4 Hz, with attenuation increas-

ing at a 20 dB per decade rate above 4 Hz. For E1

the corner frequency is approximately 1.25 Hz in

order to comply with ETSI 300 011, TBR12/13,

and recommendation I.431 Complying to these

specifications also guarantees compliance to less

stringent standards, such as G.736. Typical jitter at-

tenuation curves are shown in Figures 10 and 11.

2.7 Receiver Loss of Signal

The receiver will indicate loss of signal by assert-

ing LOS (pin 12, also CR1.0 in host mode). This

happens on power up, reset, when the receiver gain

reaches its maximum, or on receiving 175+/-15

consecutive zeros. Received zeros are counted

based on recovered clock cycles. When in the LOS

state, received data is not output from

RPOS/RNEG (RDATA); but is squelched until the

device comes out of LOS. The LOS condition is ex-

RCLK

LATN

14

1

2

3

4

5

LATN = 1 RCLK, 7.5 dB of Attenuation

LATN = 2 RCLK, 15 dB of Attenuation

LATN = 3 RCLK, 22.5 dB of Attenuation

LATN = 4 RCLK, 0 dB of Attenuation

Figure 9. LATN Pulse Width encoding

DS211PP8

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