CS61581 データシートの表示（PDF） - Cirrus Logic

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CS61581

T1/E1 Universal Line Interface

Cirrus Logic 

CS61581

2.9 Remote Loopback

Remote loopback is selected by setting RLOOP

high (pin 26 in Hardware mode, CR1.5 in Host

mode). In remote loopback, the recovered clock

and data input on RTIP and RRING are sent back

out on the line via TTIP and TRING. Selecting re-

mote loopback overrides a TAOS request. The re-

covered clock and data from the incoming signal are

also sent to RCLK, RPOS and RNEG (RDATA). Si-

multaneous selection of local and remote loopback

modes will cause a device reset to occur (see Reset).

2.10 Network Loopback

During Network Loopback (automatic remote

loopback), the data path and operation of the device

is identical to Remote Loopback, except this loop-

back mode is controlled by the transmitter at the

other end of the loop. It is initiated by enabling Net-

work Loopback detection on the device. In Host

Mode, Network Loopback (NLOOP) detection is

enabled by writing ones to TAOS, LLOOP and

RLOOP, then clearing them. In hardware mode,

Network Loopback can be enabled by tying

RLOOP to RCLK or by setting TAOS, LLOOP,

and RLOOP high for at least 200 ns, and then low.

Once enabled Network Loopback functionality

will remain in effect until RLOOP is activated or

the device is reset.

When NLOOP detection is enabled, the receiver

monitors the input data stream for the LOOP UP

data pattern: a repeating 00001. When this pattern

is repeated for a minimum of five seconds (with

less than 10-3 BER), the device sets its internal data

path as in Remote Loopback. It stays in this mode

until the LOOP DOWN pattern (repeating 001) is

received for 5 seconds, or by activation of RLOOP.

NLOOP is temporarily suspended by LLOOP, but

the NLOOP state is not reset.

The device can also generate the LOOP UP and

LOOP DOWN sequences by setting the LOOPUP

(CR2.3) or LOOPDN (CR2.4) bits respectively.

The Network Loopback generation and detection

functions are only available in Long Haul mode.

2.11 Alarm Indication Signal

The receiver sets the register bit, AIS, to “1” when

less than 9 zeros are detected out of 8192 bit peri-

ods. AIS returns to “0” upon the first read after the

AIS condition is removed, determined by 9 or more

zeros out of 8192 bit periods.

Some operations change the definition of other bits.

Writing a 1 or 0 to SH/LH (CR2.0 = 1), places the

device in Short Haul or Long Haul mode respec-

tively, and the definition of Control Registers 1 and

2 are modified accordingly. In Long Haul mode, E1

operation can be enabled by setting E1_LH to 1

(CR3.6 = 1), changes CR1.2 from B8ZS to HDB3.

Enabling unipolar mode by setting TNEG (pin 4) high

for 16 clocks allows the user to enable coder mode us-

ing the CODER bit (CR1.2LH). When TNEG is low,

enabling bipolar mode, CR1.2LH is the TAZ bit

(transmit all zeroes).

2.12 Serial Interface

In the Host Mode, pins 24 through 28 serve as a mi-

crocontroller interface. On-chip registers can be

written to via the SDI pin or read from via the SDO

pin at the clock rate determined by SCLK. Through

these registers, a host controller can be used to con-

trol operational characteristics and monitor device

status. The serial port read/write timing is indepen-

dent of the system transmit and receive timing.

Data transfers are initiated by taking the chip select

input, CS, low (CS must initially be high). Address

and input data bits are clocked in on the rising edge

of SCLK. The clock edge on which output data is

stable and valid is determined by CLKE as shown

in Table 2. Data transfers are terminated by setting

CS high. CS may go high no sooner than 50 ns after

the rising edge of the SCLK cycle corresponding to

the last write bit. For a serial data read, CS may go

high any time to terminate the output and set SDO

to high impedance.

16

DS211PP8

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