CS61582 データシートの表示（PDF） - Cirrus Logic
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CS61582 Datasheet PDF : 32 Pages
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APPLICATIONS
3
3
2
2
2
2
2
2
2
REFCLK 1XCLK RESET CLKE CON[0:2]1 CON[0:2]2 TAOS[1:2] LLOOP[1:2] RLOOP[1:2] LOS[1:2] MTIP[1:2] MRING[1:2] DPM[1:2]
Clock Generator
TCLK1
Hardware Control
T1 1:1.15
TTIP1 0.47µFC1
transmit
Framer
TPOS1
TNEG1
RCLK1
Channel 1
TRING1
R1
T2 1:1.15
RTIP1 0.47µF
RPOS1
receive
RNEG1
Framer
TCLK2
TPOS2
TNEG2
RCLK2
Channel 2
RRING1 R2
T3 1:1.15
TTIP2 0.47µFC2
transmit
TRING2
R3
T4 1:1.15
RTIP2
0.47µF
RPOS2
receive
RNEG2
Power Supply
RRING2
R4
AV+ AGND1:2 BGREF TGND2 TV+2 TV+1 TGND1 RGND2 RV+2 RV+1 RGND1 DV+ DGND1:3
0.1 µF 2
VCC
+
1 µF
R3
5kΩ 0.1 µF
0.1 µF
+
22 µF
0.1 µF
0.1 µF
3
0.01 µF
Figure A1. Typical Connection Diagram
Data Rate (MHz)
1.544
2.048
REFCLK Frequency (MHz)
1XCLK = 1
1XCLK = 0
1.544
12.352
2.048
16.384
Cable (Ω)
100
75
120
Table A1. CS61582 External Components
R1-R4 (Ω)
38.3
28.7
45.3
C1-C2 (pF)
220
470
220
Line Interface
Figure A1 illustrates a typical connection diagram
and Table A1 lists the external components that
are required in T1 and E1 applications.
In the transmit line interface circuitry, capacitors
C1 and C2 provide transmitter return loss. The
0.47 µF capacitor in series with the transformer
primary prevents output stage imbalances from
producing a DC current through the transformer
that might saturate the transformer and result in
an output level offset.
In the receive line interface circuitry, resistors R1-
R4 provide receive impedance matching and
receiver return loss. The 0.47 µF capacitor to
ground provides the necessary differential input
voltage reference for the receiver.
Power Supply
As shown in Figure A1, the CS61582 operates
from a 5.0 Volt supply. Separate analog and digi-
tal power supply and ground pins provide internal
isolation. The TGND, RGND, and DGND ground
pins must not be more negative than AGND. It is
recommended that all of the supply pins be con-
26
DS224PP1
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