CS61583 データシートの表示（PDF） - Cirrus Logic

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CS61583

Dual T1/E1 Line Interface

Cirrus Logic 

CS61583

TCLK1, TCLK2 : Transmit Clock (PLCC pins 13, 56; TQFP pins 4, 45)

TPOS1, TPOS2 : Transmit Positive Data (PLCC pins 14, 55; TQFP pins 5, 44)

TNEG1, TNEG2 : Transmit Negative Data (PLCC pins 15, 54; TQFP pins 6, 43)

The transmit clock and data are input to these pins. The signal is driven to the line interface at

TTIP and TRING. Data at TPOS and TNEG are sampled on the falling edge of TCLK. An

input at TPOS causes a positive pulse to be transmitted at TTIP and TRING, while an input at

TNEG causes a negative pulse to be transmitted at TTIP and TRING.

TDATA1, TDATA2 : Transmit Positive Data (PLCC pins 14, 55; TQFP pins 5, 44)

In coder mode (CODER = 1), the un-encoded digital data stream is input on TDATA in NRZ

format. Data at TDATA is sampled on the falling edge of TCLK.

TTIP1, TTIP2 : Transmit Tip (PLCC pins 20, 49; TQFP pins 11, 38)

TRING1, TRING2 : Transmit Ring (PLCC pins 23, 46; TQFP pins 14, 35)

The transmit AMI signal to the line interface is output on these pins. The transmit clock and

data are input from TCLK, TPOS, and TNEG (or TDATA).

Oscillator

1XCLK : One-times Clock Frequency Select (PLCC pin 38; TQFP pin 28)

When 1XCLK is set high, REFCLK must be a 1X clock (i.e., 1.544 MHz for T1 or 2.048 MHz

for E1 applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e., 12.352

MHz for T1 or 16.384 MHz for E1 applications).

REFCLK : External Reference Clock Input (PLCC pin 36, TQFP pin 26)

Input reference clock for the receive and jitter attenuator circuits. When 1XCLK is high,

REFCLK must be a 1X clock (i.e., 1.544 MHz ±100 ppm for T1 applications or 2.048 MHz

±100 ppm for E1 applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e.,

12.352 MHz ±100 ppm for T1 applications or 16.384 MHz ±100 ppm for E1 applications). The

REFCLK input also determines the transmission rate when TAOS is asserted.

Control

AMI1, AMI2 : Encoder/Decoder Select (PLCC pins 61, 52; TQFP pins 49, 41)

Setting AMI low enables the B8ZS or HDB3 zero substitution in the transmitter encoders and

receiver decoders. Setting AMI high enables AMI encoders and decoders. The AMI pins are

enabled by setting the corresponding CODER pin high.

ATTEN0, ATTEN1 : Jitter Attenuator Select (PLCC pins 25, 8; TQFP pins 16, 64)

Selects the jitter attenuation path for both channels (transmit/receive/neither).

CLKE : Clock Edge (PLCC pin 44; TQFP pin 33)

Controls the polarity of the recovered clock RCLK. When CLKE is high, RPOS and RNEG are

valid on the falling edge of RCLK. When CLKE is low, RPOS and RNEG are valid on the

rising edge of RCLK.

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DS172PP5

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