CS61583 データシートの表示（PDF） - Cirrus Logic
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CS61583 Datasheet PDF : 44 Pages
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CS61583
SWITCHING CHARACTERISTICS - T1 CLOCK/DATA (TA = -40 to 85 °C; power supply
pins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)
Parameter
Symbol Min
Typ
Max Units
TCLK Frequency
(Note 25) ftclk
-
1.544
-
MHz
TCLK Duty Cycle
tpwh2/tpw2 30
50
70
%
RCLK Duty Cycle
(Note 26) tpwh1/tpw1 45
50
55
%
Rise Time (All Digital Outputs)
(Note 27) tr
-
-
65
ns
Fall Time (All Digital Outputs)
(Note 27) tf
-
-
65
ns
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
tsu1
-
274
-
ns
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
th1
-
274
-
ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
-
-
ns
Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. For the gapped clock to be
tolerated by the CS61583, the jitter attenuator must be switched to the transmit path of the line
interface. The maximum gap size that can be tolerated on TCLK is 28 UIp-p.
26. RCLK duty cycle may be outside the specified limits when the jitter attenuator is in the receive path,
and when the jitter attenuator is employing the overflow/underflow protection mechanism.
27. At max load of 50 pF.
SWITCHING CHARACTERISTICS - E1 CLOCK/DATA (TA = -40 to 85 °C; power supply
pins within ±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)
Parameter
Symbol Min
TCLK Frequency
(Note 25) ftclk
-
TCLK Duty Cycle
tpwh2/tpw2 30
RCLK Duty Cycle
(Note 26) tpwh1/tpw1 45
Rise Time (All Digital Outputs)
(Note 27) tr
-
Fall Time (All Digital Outputs)
(Note 27) tf
-
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
tsu1
-
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
th1
-
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
Typ
2.048
50
50
-
-
194
194
-
-
Max Units
-
MHz
70
%
55
%
65
ns
65
ns
-
ns
-
ns
-
ns
-
ns
6
DS172PP5
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