CS61584A データシートの表示（PDF） - Cirrus Logic
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CS61584A Datasheet PDF : 54 Pages
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DS261PP5
CS61584A
DIGITAL CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal.)
Parameter
Symbol
Min
Max
Unit
High-Level Input Voltage
(Note 23) VIH
(DV+) - 0.5
-
V
Low-Level Input Voltage
(Note 23)
VIL
-
0.5
V
High-Level Output Voltage (Iout = -40 µA)
(Note 24) VOH
(DV+) - 0.3
-
V
Low-Level Output Voltage (Iout = 1.6 mA)
(Note 24) VOL
-
0.3
V
Input Leakage Current (Digital pins except J-TMS and J-TDI)
-
±10
µA
Notes: 23. Digital inputs are designed for CMOS logic levels.
24. Digital outputs are TTL compatible and drive CMOS levels into a CMOS load.
SWITCHING CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal;
Inputs: Logic 0 = 0 V, Logic 1 = DV+.)
Parameter
Symbol Min
T1 Clock/Data
TCLK Frequency
(Note 25)
ftclk
-
TCLK Duty Cycle
tpwh2/tpw2
20
RCLK Duty Cycle
(Note 26) tpwh1/tpw1
45
Rise Time (All Digital Outputs)
(Note 27)
tr
-
Fall Time (All Digital Outputs)
(Note 27)
tf
-
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
tsu1
-
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
th1
-
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
E1 Clock/Data
TCLK Frequency
(Note 25)
ftclk
-
TCLK Duty Cycle
tpwh2/tpw2
20
RCLK Duty Cycle
(Note 26) tpwh1/tpw1
45
Rise Time (All Digital Outputs)
(Note 27)
tr
-
Fall Time (All Digital Outputs)
(Note 27)
tf
-
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
tsu1
-
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
th1
-
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
Typ
1.544
50
50
-
-
274
274
-
-
2.048
50
50
-
-
194
194
-
-
Max Unit
-
MHz
80
%
55
%
65
ns
65
ns
-
ns
-
ns
-
ns
-
ns
-
MHz
80
%
55
%
65
ns
65
ns
-
ns
-
ns
-
ns
-
ns
Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. For the gapped clock to be
tolerated by the CS61584A, the jitter attenuator must be switched to the transmit path of the line
interface. The maximum gap size that can be tolerated on TCLK is 28 UIp-p.
26. RCLK duty cycle may be outside the specified limits when the jitter attenuator is in the transmit path
and when the jitter attenuator is employing the overflow/underflow protection mechanism.
27. At max load of 50 pF.
8
DDS2S6216P1PF15
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