CS7615-KQ データシートの表示（PDF） - Cirrus Logic
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CS7615-KQ Datasheet PDF : 36 Pages
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CS7615
Symbol
VLO
VLE
VBO
XSO
VBE
XSE
Description
# of lines in odd field
# of lines in even field
End of VREF line #
Charge transfer line #
End of VREF line #
Charge transfer line #
Register
33h, 39h
34h, 39h
36h, 39h
38h, 39h
35h, 39h
37h, 39h
Table 1. CCD vertical timing specifications
Table 2 specifies all of the programmable timing
parameters related to horizontal timing signals.
These parameters are defined in Figure 9.
Figure 9 shows the timings for HREF, HSYNC,
CLAMP, and HENB. Their relationship to differ-
ent kinds of pixels on each horizontal row output
from the CCD is also shown. The waveforms for
these signals are repeated on every line. The hori-
zontal shift register clocks, H1 and H2, operate at
the CLKO frequency and are active throughout the
horizontal line period except when HENB is high.
Figure 10 shows the timings for the V1X through
V4X signals. The specified waveforms repeat on
every horizontal line except during the charge
transfer line. During this line the CCD charge is
read out and the timing is different as shown in Fig-
ure 11. In addition signals VH1X and VH3X are
also required during charge read out as shown in
Figure 12.
The overflow drain control signal is shown in Fig-
ure 13. The OFDX signal is used to control the
electronic shutter timing of the CCD. Shutter tim-
ing for various settings of the shutter control is de-
scribed in the register section of this document.
Description of Operation
The internal operation of the CS7615 can be sepa-
rated into several distinct blocks. The following
section provides an overview of how these blocks
operate and interact.
Automatic Gain Control
The pixel data entering the CS7615 from the CCD
is scaled as determined by the automatic gain con-
trol loop. By properly applying gain to the signal,
the full range of the A/D converter is used. The in-
VREF*
1
VLO
VBO: end of VREF
VLE
VBE: end of VREF
HREF
FLD
XSO: charge transfer line
Not to scale
XSE: charge transfer line
Figure 8. Vertical Timing Signals -Internal to CS7615
DS231PP6
9
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