CS7620 データシートの表示（PDF） - Cirrus Logic

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CS7620

CCD Imager Analog Processor

Cirrus Logic 

CS7620

2 GENERAL DESCRIPTION

The CS7620 forms the heart of a four chip digital

CCD Camera. The four chips include the CCD im-

ager, the CS7620 CCD digitizer, a vertical drive in-

terface chip and a backend DSP chip to further

process the digital data (see Figure 4.) The CS7620

has a built-in timing generator which works with

imagers from IBM and Polaroid. If other CCDs are

used, the internal timing generator can be bypassed

and replaced by an external device, which outputs

the appropriate timing signals.

The patented DRX technology allows the CS7620

to output data with 13-bit dynamic range, and at the

same time reducing the power consumption to a 10-

bit equivalent A/D converter.

The digitized output is either available in 13-bits,

12-bits or 10-bits. The 10-bit output is created by

companding the 13-bit A/D output to 10-bits. The

companding curve consists of 4 linear segments,

where each slope and each start point is user pro-

grammable. Two output control signals and one

output clock provide synchronization with the out-

put data.

A block diagram of the CS7620 chip is shown in

Figure 5.

CCD

CS7620

CDS/ADC

Timing Control

Backend

DSP

Video Output

Vertical Drive

LCD Panel

+5 V to -5 V

+5 V

DC-DC converter

Figure 4. Digital Camera Block Diagram

AIN

Σ

CDS/VGA

A/D

RG

H1

Analog

H2

Clock

H3

Generator

H4

CLOCK_IN

PLL

Black

Level

Gain

Adjust

13 to 10-bit

Compander

M

U

X

Reference

VDD[5]

GND[5]

DOUT[12:0]

(up to 3 may be unused)

CLKO

CLAMP

SCAN_MODE

PWR_DN

RST

TEST

REF_CAPP

1 µF

REF_CAPN

BG_RES

10 kΩ

BYPASS_PLL

DIAG[1:0]

DAC1

DAC2

Serial Interface

Timing

Generator

LINE_ENA

EXPOSE

HSYNC

RD_OUT

DAC_OUT1 DAC_OUT2 SEN SDATI SDATO SCLK V1 V2 V3 V4 S1 S2 S3 S4

Figure 5. CS7620 Block Diagram

8

DS301PP2

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