CS7622 データシートの表示（PDF） - Cirrus Logic
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CS7622 Datasheet PDF : 36 Pages
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CS7622
1Fh to 1fh and set register 20h to ffh) and setting
slope1 to 32 (set register 15h to 00010xxxb and set
register 16h to 20h). Once the statistics have been
gathered, all four registers should be returned to
their previous values before taking the actual pic-
ture.
The output of the compander is available at the pins
DOUT<9:0> and it makes transitions either at the
falling or rising edges of the pixel rate clock CL-
KO, controlled by a register bit. The Falling edge
option is shown in Figure 14.
3.5 Stand By and Preview Mode
In order to enter power down mode a value of 07h
must be written to register 01h. This will power
down all the analog sections. Stopping the input
clocks will power down the digital. To power up
again, the input clocks must be turned on first then
a value of 00h needs to be written to register 01h.
The user must wait at least 500µs for the internal
analog references to settle to their appropriate val-
ues before normal operation is resumed. It is
strongly recommend that the chip should be kept in
Stand By mode when not in use in order to save
power. When in preview mode, a user may wish to
cut down the resolution of the ADC output to 6 bits
in order to reduce the power consumption of the
CS7622. In this mode, the current is reduced by
20 mA. With the DRX (Dynamic Range eXten-
sion) circuitry, 3 bits of dynamic range are added to
the 6-bit ADC output producing a 9-bit output. The
pins DOUT[12:4] are used to output the digitized
data in preview or Stand By mode.
3.6 Serial Interface
The serial interface is designed to allow high speed
input to control the chip’s registers. The specifica-
tions on this interface are as follows:
Asserting the enable pin, SEN, enables the serial
interface to perform data transfers. Data present on
the SDATI pin is latched into the CS7622 on each
rising edge of the serial clock, SCLK. Data output
on SDATO from the CS7622 is clocked out on the
rising edge of SCLK.
CLKO
DOUT<9:0>
CCD
INPUT
SIGNAL
CK_FT
CK_DT
14
Figure 14. CS7622 output data and clocks
T1
T4
T3
T2
Figure 15. Input Timing
DS322PP1
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