CS61305A データシートの表示（PDF） - Cirrus Logic
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CS61305A Datasheet PDF : 44 Pages
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CS61305A
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Min
Typ
Max
Units
Transmitter Jitter Attenuator
Jitter Attenuation Curve Corner Frequency (Notes 16, 19)
-
3
-
Hz
Attenuation at 10kHz Jitter Frequency
(Notes 16, 19)
-
50
-
dB
Attenuator Input Jitter Tolerance
(Notes 16, 19)
138
-
(Before Onset of FIFO Overflow or Underflow Protection)
-
UI
Receiver
RTIP/RRING Input Impedance
Sensitivity Below DSX (0dB = 2.4V)
-
50k
-13.6
-
500
-
-
Ω
-
dB
-
mV
Data Decision Threshold
T1, DSX-1
(Note 20)
53
65
77
% of peak
T1, (FCC Part 68) and E1
(Note 21)
45
50
55
% of peak
Allowable Consecutive Zeros before LOS
160
175
190
bits
Receiver Input Jitter Tolerance
10kHz - 100kHz
2kHz
10Hz and below
(Note 22)
0.4
-
6.0
-
300
-
-
UI
-
UI
-
UI
Loss of Signal Threshold
-
0.30
-
V
Notes: 19. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates
jitter at 20 dB/decade above the corner frequency. See Figure 10. Output jitter can increase
significantly when more than 12 UI’s are input to the attenuator. See discussion in the text section.
20. For input amplitude of 1.2 Vpk to 4.14 Vpk.
21. For input amplitude of 1.05 Vpk to 3.3 Vpk.
22. Jitter tolerance increases at lower frequencies. See Figure 12.
E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Crystal Frequency
ACLKI Duty Cycle
ACLKI Frequency
RCLK Cycle Width
Parameter
(Note 23)
(Note 24)
(Note 25)
Rise Time, All Digital Outputs
(Note 26)
Fall Time, All Digital Outputs
(Note 26)
TCLK Frequency
TCLK Pulse Width
(Notes 27, 28)
(Notes 29, 30)
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
(Note 27)
RDATA Valid Before RCLK Falling
(Note 29)
RPOS/RNEG Valid Before RCLK Rising
(Note 28)
RPOS/RNEG Valid After RCLK Falling
(Note 27)
RDATA Valid After RCLK Falling
(Note 29)
RPOS/RNEG Valid After RCLK Rising
(Note 28)
Symbol
fc
tpwh3/tpw3
faclki
tpw1
tpwh1
tpwl1
tr
tf
ftclk
tpwh2
tsu2
th2
tsu1
tsu1
tsu1
th1
th1
th1
Min
Typ
Max Units
-
8.192000 -
MHz
40
-
60
%
-
2.048
-
MHz
310
488
620 ns
90
140
190 ns
120
348
500 ns
-
-
85
ns
-
-
85
ns
-
2.048
-
MHz
80
-
-
ns
150
-
340 ns
25
-
-
ns
25
-
-
ns
100
194
-
ns
100
194
-
ns
100
194
-
ns
100
194
-
ns
100
194
-
ns
100
194
-
ns
4
DS157PP3
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