CDB8420 データシートの表示（PDF） - Cirrus Logic
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CDB8420 Datasheet PDF : 94 Pages
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DIGITAL INPUT CHARACTERISTICS
CS8420
Parameters
Input Leakage Current
Differential Input Voltage, RXP to RXN
Symbol Min Typ Max Units
Iin
-
±10 ±15
μA
VTH
200
-
-
mVpp
DIGITAL INTERFACE SPECIFICATIONS
AGND = DGND = 0 V; all voltages with respect to 0 V.
Parameters
High-Level Output Voltage (IOH = -3.2 mA), except TXP/TXN
Low-Level Output Voltage (IOH = 3.2 mA), except TXP/TXN
High-Level Output Voltage (IOH = -21 mA), TXP, TXN
Low-Level Output Voltage (IOH = 21 mA), TXP, TXN
High-Level Input Voltage, except RXP, RXN
Low-Level Input Voltage, except RXP, RXN
Symbol
VOH
VOL
VIH
VIL
Min
Max
(VD+) - 1.0
-
-
0.4
(VD+) - 0.7
-
-
0.7
2.0 (VD+) + 0.3
-0.3
0.8
Units
V
V
V
V
V
V
TRANSMITTER CHARACTERISTICS
Parameters
TXP Output Resistance
TXN Output Resistance
Symbol
Typ
RTXP
25
RTXN
25
Units
Ω
Ω
SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.
Parameter
RST pin Low Pulse Width
OMCK Frequency for OMCK = 512 * Fso
OMCK Low and High Width for OMCK = 512 * Fso
Symbol Min Typ
200
-
4.096
-
8.2
-
Max
-
55.3
-
Units
μs
MHz
ns
OMCK Frequency for OMCK = 384 * Fso
3.072
-
41.5 MHz
OMCK Low and High Width for OMCK = 384 * Fso
OMCK Frequency for OMCK = 256 * Fso
12.3
-
2.048
-
-
ns
27.7 MHz
OMCK Low and High Width for OMCK = 256 * Fso
PLL Clock Recovery Sample Rate Range
16.4
-
-
ns
8.0
-
108.0 kHz
RMCK output jitter
(Note 5)
-
200
-
ps RMS
RMCK output duty cycle
RMCK Input Frequency
(Note 6)
40
50
60
%
2.048
-
27.7 MHz
RMCK Input Low and High Width
AES3 Transmitter Output Jitter
(Note 6)
16.4
-
-
ns
-
-
1
ns
5. Cycle-to-cycle jitter using 32-96 kHz external PLL components.
6. PLL is bypassed (RXD1:0 bits in the Clock Source Control register set to 10b), clock is input to the RMCK
pin.
8
DS245F4
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