CDB8420 データシートの表示（PDF） - Cirrus Logic
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CDB8420 Datasheet PDF : 94 Pages
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SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.
Parameter
Symbol Min Typ
OSCLK Active Edge to SDOUT Output Valid
SDIN Setup Time Before ISCLK Active Edge
SDIN Hold Time After ISCLK Active Edge
Master Mode
(Note 7) tdpd
(Note 7)
tds
(Note 7)
tdh
-
-
20
-
20
-
O/RMCK to I/OSCLK active edge delay
O/RMCK to I/OLRCK delay
I/OSCLK and I/OLRCK Duty Cycle
(Note 7, 8) tsmd
(Note 9) tlmd
0
-
0
-
-
50
Slave Mode
I/OSCLK Period
(Note 10) tsckw
36
-
I/OSCLK Input Low Width
tsckl
14
-
I/OSCLK Input High Width
tsckh
14
-
I/OSCLK Active Edge to I/OLRCK Edge
tlrckd
20
-
(Note 7, 9, 11)
I/OLRCK Edge Setup Before I/OSCLK Active Edge
tlrcks
20
-
(Note 7, 9, 12)
CS8420
Max Units
25
ns
-
ns
-
ns
16
ns
17
ns
-
%
-
ns
-
ns
-
ns
-
ns
-
ns
7. The active edges of ISCLK and OSCLK are programmable.
8. When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising edge.
When these signals are derived from RMCK, they are clocked from its falling edge.
9. The polarity of ILRCK and OLRCK is programmable.
10. No more than 128 SCLK per frame.
11. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
has changed.
12. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has changed.
ISCLK
OSCLK
(output)
ILRCK
OLRCK
(output)
t smd
RMCK
(output)
RMCK
(output)
OMCK
(input)
Hardware Mode
Software Mode
t lmd
Figure 1. Audio Port Master Mode Timing
ILRCK
OLRCK
(input)
ISCLK
OSCLK
(input)
t lrckd
t lrcks
t sckh
t sckl
t sckw
SDIN
SDOUT
tds
tdh
tdpd
Figure 2. Audio Port Slave Mode and Data Input Timing
DS245F4
9
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