CXG1096FN データシートの表示（PDF） - Sony Semiconductor
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CXG1096FN Datasheet PDF : 7 Pages
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CXG1096FN
2. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer (Ta = 25°C)
GC, NF vs. PLO
VDD = 3V, RF1 = 1.90GHz/small signal,
LO = 1.66GHz
When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V
When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V
The data shown below is common to ANT1 and ANT2.
22
5.50
21
GC
20
5.25
5.00
19
4.75
18
4.50
NF
17
4.25
16
–25
–20 –15 –10
–5
PLO – Local input [dBm]
4.00
0
Input IP3, PLK vs. PLO
VDD = 3V, RF = 1.90GHz/–35dBm,
LO = 1.66GHz
When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V
When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V
Input IP3 is common to ANT1 and ANT2.
–10
–30
Input IP3
–12
–35
–14
–40
–16
–45
ANT1
–18
–50
–20
–22
–25
ANT2
–20
–15 –10
–5
PLO – Local input [dBm]
–55
–60
0
POUT, PIM3 vs. PIN
VDD = 3V, RF1 = 1.9000GHz, RF2 = 1.9006GHz,
LO = 1.66GHz/–15dBm
When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V
When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V
The data shown below is common to ANT1 and ANT2.
20
0
POUT
–20
–40
PIM3
–60
–80
Input IP3
–100
–50
–40
–30
–20
–10
0
PIN – RF input power [dBm]
–5–
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