CY14B101LA(2011) データシートの表示（PDF） - Cypress Semiconductor
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CY14B101LA Datasheet PDF : 26 Pages
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CY14B101LA
CY14B101NA
AC Switching Characteristics
Parameters
Cypress
Parameter
Alt
Parameter
SRAM Read Cycle
tACE
tACS
tRC[16]
tRC
tAA[17]
tAA
tDOE
tOE
tOHA[17]
tOH
tLZCE[18, 19]
tLZ
tHZCE[18, 19]
tHZ
tLZOE[18, 19]
tOLZ
tHZOE[18, 19]
tOHZ
tPU[18]
tPA
tPD[18]
tPS
tDBE[[18]
-
tLZBE[18]
-
tHZBE[18]
-
SRAM Write Cycle
tWC
tWC
tPWE
tWP
tSCE
tCW
tSD
tDW
tHD
tDH
tAW
tAW
tSA
tAS
tHA
tWR
tHZWE[18, 19, 20] tWZ
tLZWE[18, 19]
tOW
tBW
-
Description
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
Byte enable to output active
Byte disable to output inactive
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
20 ns
Min Max
–
20
20
–
–
20
–
10
3
–
3
–
–
8
0
–
–
8
0
–
–
20
–
10
0
–
–
8
20
–
15
–
15
–
8
–
0
–
15
–
0
–
0
–
–
8
3
–
15
–
25 ns
Min Max
–
25
25
–
–
25
–
12
3
–
3
–
–
10
0
–
–
10
0
–
–
25
–
12
0
–
–
10
25
–
20
–
20
–
10
–
0
–
20
–
0
–
0
–
–
10
3
–
20
–
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled [16, 17, 21]
tRC
Address
Address Valid
tAA
45 ns
Min Max
–
45
45
–
45
–
20
3
–
3
–
–
15
0
–
–
15
0
–
–
45
–
20
0
–
15
45
–
30
–
30
–
15
–
0
–
30
–
0
–
0
–
–
15
3
–
30
–
Data Output
Previous Data Valid
tOHA
Output Data Valid
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
16. WE must be HIGH during SRAM read cycles.
17. Device is continuously selected with CE, OE, and BHE/BLE LOW.
18. These parameters are guaranteed by design and are not tested.
19. Measured ±200 mV from steady state output voltage.
20. If WE is low when CE goes low, the outputs remain in the high impedance state.
21. HSB must remain HIGH during Read and Write cycles.
Document #: 001-42879 Rev. *K
Page 11 of 26
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