CY14B101LA-SZ25XIT(2011) データシートの表示（PDF） - Cypress Semiconductor
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CY14B101LA-SZ25XIT Datasheet PDF : 26 Pages
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CY14B101LA
CY14B101NA
Pinouts (continued)
Figure 3. 48-Ball FBGA and 54-Pin TSOP II
48-FBGA
(x8)
Top View
(not to scale)
12
3
4
5
6
NC OE A0 A1 A2 NC
A
NC NC A3 A4 CE NC
B
DQ0 NC A5 A6 NC DQ4
C
VSS DQ1 NC[4] A7 DQ5 VCC
D
VCC DQ2 VCAP A16 DQ6 VSS
E
DQ3 NC A14 A15 NC DQ7
F
NC HSB A12 A13 WE NC
G
[5]
NC
A8
A9
A10
A11
[6]
NC
H
NC
[7]
1
NC 2
A0 3
A1 4
54 HSB
53 NC [6]
52 NC[5]
51 NC[4]
A2 5
A3 6
50 A15
49 OE
A4 7
48 BHE
CE 8
47 BLE
DQ0 9
46 DQ15
DQ1 10 54 - TSOP II 45
DQ2 11
(x16)
44
DQ3 12
43
VCC 13
Top View
42
VSS 14 (not to scale) 41
DQ4 15
40
DQ5 16
39
DQ6 17
38
DQ7 18
37
WE 19
36
A5 20
35
A6 21
34
A7 22
33
A8 23
32
A9 24
31
NC 25
30
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
NC
NC 26
29 NC
NC 27
28 NC
Table 1. Pin Definitions
Pin Name I/O Type
Description
A0 – A16
A0 – A15
Input
Address inputs. Used to select one of the 131,072 bytes of the nvSRAM for x8 configuration.
Address inputs. Used to select one of the 65,536 words of the nvSRAM for x16 configuration.
DQ0 – DQ7 Input/Output Bidirectional data I/O lines for ×8 configuration. Used as input or output lines depending on operation.
DQ0 – DQ15
Bidirectional Data I/O Lines for ×16 configuration. Used as input or output lines depending on operation.
WE
Input Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE
Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tristated on deasserting OE HIGH.
BHE
BLE
VSS
VCC
HSB[8]
Input
Input
Ground
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Ground for the device. Must be connected to the ground of the system.
Power Power supply inputs to the device. 3.0 V +20%, –10%
supply
Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
VCAP
NC
Power AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvol-
supply atile elements.
No connect No connect. This pin is not connected to the die.
Document #: 001-42879 Rev. *K
Page 4 of 26
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